公开(公告)号：US20140175490A1

公开(公告)日：2014-06-26

申请号：US14127837

申请日：2012-06-12

Applicant: Yuji Suwa ,  Shinichi Saito ,  Etsuko Nomoto ,  Makoto Takahashi

Inventor： Yuji Suwa ,  Shinichi Saito ,  Etsuko Nomoto ,  Makoto Takahashi

IPC: H01L33/36

CPC classification number: H01L33/36 ,  H01L33/0054 ,  H01L33/06 ,  H01L33/20 ,  H01L33/34 ,  H01S5/0424 ,  H01S5/1032 ,  H01S5/3224

Abstract: Provided is an element structure whereby it is possible to produce a silicon-germanium light-emitting element enclosing an injected carrier within a light-emitting region. Also provided is a method of manufacturing the structure. Between the light-emitting region and an electrode there is produced a narrow passage for the carrier, specifically, a one-dimensional or two-dimensional quantum confinement region. A band gap opens up in this section due to the quantum confinement, thereby forming an energy barrier for both electrons and positive holes, and affording an effect analogous to a double hetero structure in an ordinary Group III-V semiconductor laser. Because no chemical elements other than those used in ordinary silicon processes are employed, the element can be manufactured inexpensively, simply by controlling the shape of the element.

Abstract translation: 提供了一种元件结构，由此可以在发光区域内产生包围注入载体的硅锗发光元件。 还提供了一种制造该结构的方法。 在发光区域和电极之间，为载体产生窄通道，具体地说，是一维或二维量子限制区域。 由于量子限制，在该部分中带隙打开，由此形成电子和空穴的能量势垒，并且提供类似于普通III-V族半导体激光器中的双异质结构的效果。 由于不使用在普通硅工艺中使用的化学元素以外的化学元素，所以可以通过简单地控制元件的形状来廉价地制造元件。

公开(公告)号：US08396702B2

公开(公告)日：2013-03-12

申请号：US12569142

申请日：2009-09-29

Applicant: Kenji Nagase ,  Eiji Ohta ,  Yuji Suwa ,  Toshiro Sato ,  Atsushi Takeuchi ,  Kumiko Teramae

Inventor： Kenji Nagase ,  Eiji Ohta ,  Yuji Suwa ,  Toshiro Sato ,  Atsushi Takeuchi ,  Kumiko Teramae

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5018

Abstract: An analyzing apparatus includes a result-data storing unit that determines whether result data that is calculated as a result of analysis is restorable by linear interpolation. If the result data is determined to be unrestorable by the linear interpolation, the result-data storing unit stores the result data in a predetermined storage unit. Moreover, the analyzing apparatus includes a data restoring unit that reads the result data from the storage unit. The data restoring unit performs the linear interpolation using the result data acquired, thereby restoring the result data.

Abstract translation: 分析装置包括结果数据存储单元，其确定作为分析结果计算的结果数据是否可通过线性内插来恢复。 如果通过线性内插确定结果数据不可恢复，则结果数据存储单元将结果数据存储在预定的存储单元中。 此外，分析装置包括从存储单元读取结果数据的数据恢复单元。 数据恢复单元使用获取的结果数据执行线性插值，从而恢复结果数据。

公开(公告)号：US07634391B2

公开(公告)日：2009-12-15

申请号：US11583889

申请日：2006-10-20

Applicant: Yuji Suwa ,  Jiro Yoneda

Inventor： Yuji Suwa ,  Jiro Yoneda

IPC: G06F17/10

CPC classification number: G06F17/5036

Abstract: An IBIS correction tool which can be used assembled in a waveform simulation device and corrects IBIS data for a certain specific power supply voltage V0 to IBIS data for a desired power supply voltage V1 with a higher precision than the past, that is, an IBIS correction tool configured so as to read IBIS data for a power supply voltage V0 as numerical data of x-y coordinates at a data input unit, find a relative ratio (correction coefficient) between this numerical data and numerical data for a power supply voltage V1 on its x-y coordinates at a correction coefficient calculating unit, and obtain corrected IBIS data corrected for the power supply voltage V1 according to that correction coefficient at a corrected IBIS data generating unit.

Abstract translation: IBIS校正工具可用于组装在波形仿真装置中，并以比以往更高的精度为IBIS数据校正IBIS数据，以获得所需电源电压V1的特定电源电压V0至IBIS数据，即IBIS校正 工具被配置为在数据输入单元处读取作为xy坐标的数值数据的电源电压V0的IBIS数据，找到该数值数据与其xy上的电源电压V1的数值数据之间的相对比率（校正系数） 在校正系数计算单元处的坐标，并且根据在校正IBIS数据生成单元处的校正系数获得针对电源电压V1校正的校正IBIS数据。

公开(公告)号：US20080315191A1

公开(公告)日：2008-12-25

申请号：US12128993

申请日：2008-05-29

Applicant: Tomihiro Hashizume ,  Yuji Suwa ,  Masaaki Fujimori ,  Tadashi Arai ,  Takeo Shiba

Inventor： Tomihiro Hashizume ,  Yuji Suwa ,  Masaaki Fujimori ,  Tadashi Arai ,  Takeo Shiba

IPC: H01L51/30 ,  H01L21/70

CPC classification number: H01L27/283 ,  H01L51/0003 ,  H01L51/0018 ,  H01L51/0021

Abstract: An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.

Abstract translation: 通过使用用于施加半导体和电极的界面和电极之间的费米能量的差异的大小的方程式，仅选择性地改变覆盖涂层而不改变TFT材料来实现n型TFT和p型TFT 半导体和绝缘体的界面。 此时，为了构成规定的电路，作为p型TFT的源电极和漏电极，n型TFT的源电极和漏极全部分别连接，进行该处理 并且通过使用扫描激光曝光装置等照射光而切断不必要的互连。

公开(公告)号：US20050098882A1

公开(公告)日：2005-05-12

申请号：US11017785

申请日：2004-12-22

Applicant: Toshihiro Kusagaya ,  Yasuhiro Yoneda ,  Daisuke Mizutani ,  Kazuhiko Iijima ,  Yuji Suwa

Inventor： Toshihiro Kusagaya ,  Yasuhiro Yoneda ,  Daisuke Mizutani ,  Kazuhiko Iijima ,  Yuji Suwa

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H01L21/44 ,  H01L23/48 ,  H01L29/76 ,  H01L31/062

CPC classification number: H05K3/4641 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/01087 ,  H05K1/0216 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1394

Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.

Abstract translation: 能够通过降低所提供的电路的电感来抑制在产生高频噪声的同时对电路进行高频开关动作的便宜的多层布线电路板。 一种多层布线电路板，包括：被指定为第一层的最上层，其上安装有部件; 布置有接地层和电源层中的一个的第二层; 另一个排列在其上的第三层; 以及布置在接地层和电源层之间的绝缘层。 作为在电源层和接地层之间配置的绝缘层的材料，使用两面具有热塑性粘合性的树脂层。

公开(公告)号：US06780698B2

公开(公告)日：2004-08-24

申请号：US10194253

申请日：2002-07-15

Applicant: Yuji Suwa ,  Tomihiro Hashizume ,  Ken Yamaguchi ,  Masaaki Fujimori

Inventor： Yuji Suwa ,  Tomihiro Hashizume ,  Ken Yamaguchi ,  Masaaki Fujimori

IPC: H01L218238

CPC classification number: H01L29/66537 ,  H01L21/3003 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.

Abstract translation: 一种制造半导体器件的方法，包括使存在于半导体衬底中的掺杂剂在所述半导体衬底的表面中分离，从而形成具有比所述衬底更高掺杂剂浓度的薄层。 通过偏析形成的薄层防止由于MOSFET的小型化而发生的穿通。 该方法允许经济的δ掺杂，而不牺牲器件特性。

公开(公告)号：US08008654B2

公开(公告)日：2011-08-30

申请号：US12155801

申请日：2008-06-10

Applicant: Takeo Shiba ,  Tomihiro Hashizume ,  Yuji Suwa ,  Tadashi Arai

Inventor： Takeo Shiba ,  Tomihiro Hashizume ,  Yuji Suwa ,  Tadashi Arai

IPC: H01L51/00

CPC classification number: H01L51/0012 ,  H01L27/283 ,  H01L51/0004 ,  H01L51/0022 ,  H01L51/0545 ,  H01L51/0558 ,  H01L51/105

Abstract: A method of manufacturing a thin-film transistor device improves performance of a complementary TFT circuit incorporated in a thin- and light-weighted image display device or a flexible electronic device, and reduces power consumption manufacturing cost. Electrodes forming n-type and p-type TFTs and an organic semiconductor are made of the same material in both types of TFT by a solution-process and/or printable process method. A first polarizable thin-film is formed on an interface between a gate insulator and a semiconductor, and a second polarizable thin film provided on an interface between source and drain electrodes and the semiconductor film. A complementary thin-film transistor device is manufactured by selectively exposing either the n-type TFT area or the p-type TFT area to light to remove the polarizing function from the first and second polarizable thin films.

Abstract translation: 薄膜晶体管器件的制造方法提高了结合在薄型和轻型图像显示器件或柔性电子器件中的互补TFT电路的性能，并降低了功耗制造成本。 形成n型和p型TFT的电极和有机半导体通过溶液处理和/或可印刷的方法在两种类型的TFT中由相同的材料制成。 第一可极化薄膜形成在栅极绝缘体和半导体之间的界面上，第二可极化薄膜设置在源电极和漏电极与半导体膜之间的界面上。 通过将n型TFT区域或p型TFT区域选择性地暴露于光以从第一和第二可极化薄膜去除偏振功能来制造互补薄膜晶体管器件。

公开(公告)号：US20080087883A1

公开(公告)日：2008-04-17

申请号：US11865769

申请日：2007-10-02

Applicant: YUJI SUWA ,  Tomihiro Hashizume ,  Masahiko Ando ,  Takeo Shiba

Inventor： YUJI SUWA ,  Tomihiro Hashizume ,  Masahiko Ando ,  Takeo Shiba

IPC: H01L51/10 ,  H01L51/30

CPC classification number: H01L51/105 ,  H01L51/0545

Abstract: Disclosed are a method for inexpensively reducing the contact resistance between an electrode and an organic semiconductor upon a p-type operation of the organic semiconductor; and a method for inexpensively operating, as an n-type semiconductor, an organic semiconductor that is likely to work as a p-type semiconductor. In addition, also disclosed are a p-cannel FET, an n-channel FET, and a C-TFT which can be fabricated inexpensively. Specifically, a p-type region and an n-type region is inexpensively prepared on one substrate by arranging an organic semiconductor that is likely to work as a p-type semiconductor in a p-channel FET region and an n-channel FET region of a C-TFT; and arranging a self-assembled monolayer between an electrode and the organic semiconductor in the n-channel FET region, which self-assembled monolayer is capable of allowing the organic semiconductor to work as an n-type semiconductor.

Abstract translation: 公开了一种在有机半导体的p型操作时廉价地降低电极和有机半导体之间的接触电阻的方法; 以及作为n型半导体廉价地操作有可能用作p型半导体的有机半导体的方法。 此外，还公开了可以廉价制造的p型FET，n沟道FET和C-TFT。 具体地说，在一个衬底上廉价地制备p型区域和n型区域，通过在p沟道FET区域和n沟道FET区域中配置可能作为p型半导体的有机半导体， 一个C-TFT; 并且在n沟道FET区域中的电极和有机半导体之间布置自组装单层，该自组装单层能够使有机半导体作为n型半导体工作。

公开(公告)号：US20080012009A1

公开(公告)日：2008-01-17

申请号：US11685958

申请日：2007-03-14

Applicant: Tomihiro Hashizume ,  Masaaki Fujimori ,  Yuji Suwa ,  Tadashi Arai

Inventor： Tomihiro Hashizume ,  Masaaki Fujimori ,  Yuji Suwa ,  Tadashi Arai

IPC: H01L51/10 ,  H01L51/40

CPC classification number: H01L51/0021 ,  H01L51/0545 ,  H01L51/105

Abstract: A method for determining the combination of the electrode and organic semiconductor with improved electron injection efficiency and hole injection efficiency in an organic TFT is provided, two types of FETS, that is, an n channel FET and a p channel FET are realized, and further, a complementary TFT (CTFT) is provided. The method for obtaining the vacuum level shift at the electrode metal/organic semiconductor interface from physical constants of constituent elements of the electrode and the organic semiconductor is provided. By changing the electrode metal through an electrochemical method, the electrodes whose electron injection and hole injection can be controlled are formed. By using these electrodes, two types of FETs such as an n channel FET and a p channel FET are realized, thereby providing a complementary TFT (CTFT).

Abstract translation: 提供了一种用于确定电极和有机半导体在有机TFT中具有改进的电子注入效率和空穴注入效率的组合的方法，实现了两种类型的FETS，即n沟道FET和ap沟道FET，此外， 提供互补TFT（CTFT）。 提供了从电极和有机半导体的构成元件的物理常数获得电极金属/有机半导体界面处的真空电平移动的方法。 通过电化学方法改变​​电极金属，可以形成电子注入和空穴注入的电极。 通过使用这些电极，实现了诸如n沟道FET和p沟道FET的两种类型的FET，从而提供互补TFT（CTFT）。

公开(公告)号：US20070185699A1

公开(公告)日：2007-08-09

申请号：US11583889

申请日：2006-10-20

Applicant: Yuji Suwa ,  Jiro Yoneda

Inventor： Yuji Suwa ,  Jiro Yoneda

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: An IBIS correction tool which can be used assembled in a waveform simulation device and corrects IBIS data for a certain specific power supply voltage V0 to IBIS data for a desired power supply voltage V1 with a higher precision than the past, that is, an IBIS correction tool configured so as to read IBIS data for a power supply voltage V0 as numerical data of x-y coordinates at a data input unit, find a relative ratio (correction coefficient) between this numerical data and numerical data for a power supply voltage V1 on its x-y coordinates at a correction coefficient calculating unit, and obtain corrected IBIS data corrected for the power supply voltage V1 according to that correction coefficient at a corrected IBIS data generating unit.

Abstract translation: IBIS校正工具可以被组装在波形仿真装置中，并且以比以往更高的精度来校正用于期望的电源电压V 1的某一特定电源电压V 0到IBIS数据的IBIS数据，即， IBIS校正工具被配置为读取作为数据输入单元的xy坐标数字数据的电源电压V 0的IBIS数据，找到该数值数据与电源电压V的数值数据之间的相对比率（校正系数） 1，在校正系数计算单元的xy坐标上，根据在校正IBIS数据生成单元的校正系数，获得针对电源电压V 1校正的校正IBIS数据。