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公开(公告)号:US20130106518A1
公开(公告)日:2013-05-02
申请号:US13422239
申请日:2012-03-16
申请人: Yosuke OGASAWARA
发明人: Yosuke OGASAWARA
IPC分类号: H03F3/04
CPC分类号: H03F1/523 , H02H9/046 , H03F1/52 , H03F1/565 , H03F2200/267 , H03F2200/426 , H03F2200/522 , H03G1/0017
摘要: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.
摘要翻译: 根据一个实施例,提供了被配置为放大输入信号的放大器晶体管; 偏置电路,被配置为以允许放大器晶体管执行放大的方式设置偏置电压; 静电保护电路,被配置为以放大晶体管为基准的电压来设置用于放大晶体管的偏置电压,以使放大晶体管截止; 以及开关电路,被配置为基于电源条件来切换放大器晶体管的偏置电压。
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公开(公告)号:US20120134447A1
公开(公告)日:2012-05-31
申请号:US13234596
申请日:2011-09-16
申请人: Kazumi Sato , Yosuke Ogasawara
发明人: Kazumi Sato , Yosuke Ogasawara
CPC分类号: H03L7/0891 , H03L7/093 , H04L7/033
摘要: According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.
摘要翻译: 根据一个实施例,模拟单元执行接收信号的频率转换。 数字单元对通过模拟单元进行频率转换的接收信号执行解调处理。 PLL电路产生数字单元的时钟。 PLL设置改变单元基于接收信号执行PLL电路的参数的设置改变,从而控制时钟的抖动。
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公开(公告)号:US08115549B2
公开(公告)日:2012-02-14
申请号:US12539034
申请日:2009-08-11
申请人: Yosuke Ogasawara
发明人: Yosuke Ogasawara
IPC分类号: H03F3/45
CPC分类号: H03F3/45475 , H03F3/19 , H03F3/45179 , H03F2200/165 , H03F2200/451 , H03F2203/45318 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528
摘要: A feedback resistor is connected between an input terminal and an output terminal of an operational amplifier. A negative resistor is connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier.
摘要翻译: 反馈电阻连接在运算放大器的输入端和输出端之间。 负电阻连接在运算放大器的反相输入端和非反相输入端之间。
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公开(公告)号:US20110130109A1
公开(公告)日:2011-06-02
申请号:US12754748
申请日:2010-04-06
申请人: Yosuke Ogasawara
发明人: Yosuke Ogasawara
CPC分类号: H03F3/45475 , H03F3/45179 , H03F3/505 , H03F2203/45526 , H03F2203/5033
摘要: A differential amplifier circuit includes a source follower circuit to which is input one of the differential signals and a common source circuit that is connected in series with the source follower circuit and to which is input the other of the differential signals.
摘要翻译: 差分放大器电路包括:源极跟随器电路,其输入差分信号之一和与源极跟随器电路串联连接并且被输入另一个差分信号的公共源电路。
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公开(公告)号:US20100156538A1
公开(公告)日:2010-06-24
申请号:US12539034
申请日:2009-08-11
申请人: Yosuke Ogasawara
发明人: Yosuke Ogasawara
IPC分类号: H03F3/16
CPC分类号: H03F3/45475 , H03F3/19 , H03F3/45179 , H03F2200/165 , H03F2200/451 , H03F2203/45318 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528
摘要: A feedback resistor is connected between an input terminal and an output terminal of an operational amplifier. A negative resistor is connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier.
摘要翻译: 反馈电阻连接在运算放大器的输入端和输出端之间。 负电阻连接在运算放大器的反相输入端和非反相输入端之间。
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公开(公告)号:US20120105148A1
公开(公告)日:2012-05-03
申请号:US13344664
申请日:2012-01-06
申请人: Yosuke Ogasawara
发明人: Yosuke Ogasawara
IPC分类号: H03F1/34
CPC分类号: H03F3/45475 , H03F3/19 , H03F3/45179 , H03F2200/165 , H03F2200/451 , H03F2203/45318 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528
摘要: A feedback resistor is connected between an input terminal and an output terminal of an operational amplifier. A negative resistor is connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier.
摘要翻译: 反馈电阻连接在运算放大器的输入端和输出端之间。 负电阻连接在运算放大器的反相输入端和非反相输入端之间。
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公开(公告)号:US09071252B2
公开(公告)日:2015-06-30
申请号:US13234596
申请日:2011-09-16
申请人: Kazumi Sato , Yosuke Ogasawara
发明人: Kazumi Sato , Yosuke Ogasawara
CPC分类号: H03L7/0891 , H03L7/093 , H04L7/033
摘要: According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.
摘要翻译: 根据一个实施例,模拟单元执行接收信号的频率转换。 数字单元对通过模拟单元进行频率转换的接收信号执行解调处理。 PLL电路产生数字单元的时钟。 PLL设置改变单元基于接收信号执行PLL电路的参数的设置改变,从而控制时钟的抖动。
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公开(公告)号:US08676148B2
公开(公告)日:2014-03-18
申请号:US12754748
申请日:2010-04-06
申请人: Yosuke Ogasawara
发明人: Yosuke Ogasawara
IPC分类号: H04B1/16
CPC分类号: H03F3/45475 , H03F3/45179 , H03F3/505 , H03F2203/45526 , H03F2203/5033
摘要: A differential amplifier circuit includes a source follower circuit to which is input one of the differential signals and a common source circuit that is connected in series with the source follower circuit and to which is input the other of the differential signals.
摘要翻译: 差分放大器电路包括:源极跟随器电路,其输入差分信号之一和与源极跟随器电路串联连接并且被输入另一个差分信号的公共源电路。
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公开(公告)号:US08581666B2
公开(公告)日:2013-11-12
申请号:US13422239
申请日:2012-03-16
申请人: Yosuke Ogasawara
发明人: Yosuke Ogasawara
IPC分类号: H03F3/04
CPC分类号: H03F1/523 , H02H9/046 , H03F1/52 , H03F1/565 , H03F2200/267 , H03F2200/426 , H03F2200/522 , H03G1/0017
摘要: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.
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