INTEGRATED CIRCUIT
    1.
    发明申请
    INTEGRATED CIRCUIT 失效
    集成电路

    公开(公告)号:US20130106518A1

    公开(公告)日:2013-05-02

    申请号:US13422239

    申请日:2012-03-16

    申请人: Yosuke OGASAWARA

    发明人: Yosuke OGASAWARA

    IPC分类号: H03F3/04

    摘要: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

    摘要翻译: 根据一个实施例,提供了被配置为放大输入信号的放大器晶体管; 偏置电路,被配置为以允许放大器晶体管执行放大的方式设置偏置电压; 静电保护电路,被配置为以放大晶体管为基准的电压来设置用于放大晶体管的偏置电压,以使放大晶体管截止; 以及开关电路,被配置为基于电源条件来切换放大器晶体管的偏置电压。

    RADIO COMMUNICATION APPARATUS
    2.
    发明申请
    RADIO COMMUNICATION APPARATUS 有权
    无线电通信设备

    公开(公告)号:US20120134447A1

    公开(公告)日:2012-05-31

    申请号:US13234596

    申请日:2011-09-16

    IPC分类号: H03D3/24 H04L27/06

    摘要: According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.

    摘要翻译: 根据一个实施例,模拟单元执行接收信号的频率转换。 数字单元对通过模拟单元进行频率转换的接收信号执行解调处理。 PLL电路产生数字单元的时钟。 PLL设置改变单元基于接收信号执行PLL电路的参数的设置改变,从而控制时钟的抖动。

    Radio communication apparatus
    7.
    发明授权
    Radio communication apparatus 有权
    无线通信装置

    公开(公告)号:US09071252B2

    公开(公告)日:2015-06-30

    申请号:US13234596

    申请日:2011-09-16

    IPC分类号: H03L7/089 H04L7/033 H03L7/093

    摘要: According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.

    摘要翻译: 根据一个实施例,模拟单元执行接收信号的频率转换。 数字单元对通过模拟单元进行频率转换的接收信号执行解调处理。 PLL电路产生数字单元的时钟。 PLL设置改变单元基于接收信号执行PLL电路的参数的设置改变,从而控制时钟的抖动。

    Differential amplifier circuit and wireless receiving apparatus
    8.
    发明授权
    Differential amplifier circuit and wireless receiving apparatus 失效
    差分放大器电路和无线接收装置

    公开(公告)号:US08676148B2

    公开(公告)日:2014-03-18

    申请号:US12754748

    申请日:2010-04-06

    申请人: Yosuke Ogasawara

    发明人: Yosuke Ogasawara

    IPC分类号: H04B1/16

    摘要: A differential amplifier circuit includes a source follower circuit to which is input one of the differential signals and a common source circuit that is connected in series with the source follower circuit and to which is input the other of the differential signals.

    摘要翻译: 差分放大器电路包括:源极跟随器电路,其输入差分信号之一和与源极跟随器电路串联连接并且被输入另一个差分信号的公共源电路。

    Integrated circuit
    9.
    发明授权

    公开(公告)号:US08581666B2

    公开(公告)日:2013-11-12

    申请号:US13422239

    申请日:2012-03-16

    申请人: Yosuke Ogasawara

    发明人: Yosuke Ogasawara

    IPC分类号: H03F3/04

    摘要: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.