公开(公告)号：US20180114776A1

公开(公告)日：2018-04-26

申请号：US15623891

申请日：2017-06-15

申请人： Won-Gil HAN ,  Byong-Joo KIM ,  Yong-Je LEE ,  Jae-Heung LEE ,  Seung-Weon HA

发明人： Won-Gil HAN ,  Byong-Joo KIM ,  Yong-Je LEE ,  Jae-Heung LEE ,  Seung-Weon HA

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/03334 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48148 ,  H01L2224/48149 ,  H01L2224/48151 ,  H01L2224/48227 ,  H01L2224/48482 ,  H01L2224/49176 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/85

摘要： A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

公开(公告)号：US08245902B2

公开(公告)日：2012-08-21

申请号：US13237345

申请日：2011-09-20

申请人： Yong-Je Lee ,  Seung-Weon Ha ,  Won-Gil Han

发明人： Yong-Je Lee ,  Seung-Weon Ha ,  Won-Gil Han

IPC分类号： B23K37/00

CPC分类号： H01L24/78 ,  H01L24/32 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/78251 ,  H01L2224/78301 ,  H01L2224/85048 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion. The apparatus further includes a first temperature sensing unit positioned to be located at a first height and to determine a first temperature at the first portion of the stack, a second temperature sensing unit positioned to be located at a second height and to determine a second temperature at the second portion of the stack, and a temperature adjusting unit configured to compare the first temperature to the second temperature and to adjust the magnitude of the heat supplied by at least one of the heater block and the chip heating unit according to a result of the comparison.

摘要翻译： 提供一种引线接合装置和使用其的半导体器件的引线接合和制造方法。 引线接合装置包括：加热块，其构造成支撑包括芯片安装框架和堆叠在芯片安装框架上的多个芯片的堆叠。 加热器块被配置为向堆叠的第一部分供应热量。 该装置还包括设置在与加热器块不同高度的芯片加热单元。 芯片加热单元被配置为以与第一部分不同的高度向堆叠的第二部分供热。 该装置还包括第一温度感测单元，其定位成位于第一高度处并且确定堆叠的第一部分处的第一温度;第二温度感测单元，定位成位于第二高度处，并且确定第二温度 在所述堆叠的第二部分处，以及温度调节单元，其被配置为将所述第一温度与所述第二温度进行比较，并且根据所述加热器块和所述芯片加热单元中的至少一个提供的热量的大小根据 比较。

公开(公告)号：US20130093080A1

公开(公告)日：2013-04-18

申请号：US13618357

申请日：2012-09-14

申请人： Won-Gil HAN ,  Se-Yeoul Park ,  Ho-Tae Jin ,  Byong-Joo Kim ,  Yong-Je Lee ,  Han-Ki Park

发明人： Won-Gil HAN ,  Se-Yeoul Park ,  Ho-Tae Jin ,  Byong-Joo Kim ,  Yong-Je Lee ,  Han-Ki Park

IPC分类号： H01L21/66 ,  H01L25/00

CPC分类号： H01L24/85 ,  H01L22/14 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4847 ,  H01L2224/48992 ,  H01L2224/4941 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/8503 ,  H01L2224/85951 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

公开(公告)号：US20120111923A1

公开(公告)日：2012-05-10

申请号：US13237345

申请日：2011-09-20

申请人： Yong-Je Lee ,  Seung-Weon Ha ,  Won-Gil Han

发明人： Yong-Je Lee ,  Seung-Weon Ha ,  Won-Gil Han

IPC分类号： B23K37/00

CPC分类号： H01L24/78 ,  H01L24/32 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/78251 ,  H01L2224/78301 ,  H01L2224/85048 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion. The apparatus further includes a first temperature sensing unit positioned to be located at a first height and to determine a first temperature at the first portion of the stack, a second temperature sensing unit positioned to be located at a second height and to determine a second temperature at the second portion of the stack, and a temperature adjusting unit configured to compare the first temperature to the second temperature and to adjust the magnitude of the heat supplied by at least one of the heater block and the chip heating unit according to a result of the comparison.

摘要翻译： 提供一种引线接合装置和使用其的半导体器件的引线接合和制造方法。 引线接合装置包括：加热块，其构造成支撑包括芯片安装框架和堆叠在芯片安装框架上的多个芯片的堆叠。 加热器块被配置为向堆叠的第一部分供应热量。 该装置还包括设置在与加热器块不同高度的芯片加热单元。 芯片加热单元被配置为以与第一部分不同的高度向堆叠的第二部分供热。 该装置还包括第一温度感测单元，其定位成位于第一高度处并且确定堆叠的第一部分处的第一温度;第二温度感测单元，定位成位于第二高度处，并且确定第二温度 在所述堆叠的第二部分处，以及温度调节单元，其被配置为将所述第一温度与所述第二温度进行比较，并且根据所述加热器块和所述芯片加热单元中的至少一个提供的热量的大小根据 比较。

公开(公告)号：US20120056178A1

公开(公告)日：2012-03-08

申请号：US13205916

申请日：2011-08-09

申请人： Won-Gil Han ,  Seung-Weon Ha ,  Yong-Je Lee ,  Han-Ki Park

发明人： Won-Gil Han ,  Seung-Weon Ha ,  Yong-Je Lee ,  Han-Ki Park

IPC分类号： H01L23/58

CPC分类号： H01L22/32 ,  H01L23/3128 ,  H01L23/5256 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A multi-chip package may include a package substrate, a plurality of semiconductor chips and conductive connecting members. The semiconductor chips may be sequentially stacked on the package substrate. Each of the semiconductor chips may include a signal pad and a test pad. The conductive wires may be electrically connected between the signal pad of an upper semiconductor chip among the semiconductor chips and the package substrate via the test pad of a lower semiconductor chip under the upper semiconductor chip. The test pad may be converted into the dummy pad by cutting a fuse.

摘要翻译： 多芯片封装可以包括封装衬底，多个半导体芯片和导电连接构件。 半导体芯片可以顺序地堆叠在封装衬底上。 每个半导体芯片可以包括信号焊盘和测试焊盘。 导电线可以通过上半导体芯片下的下半导体芯片的测试焊盘电连接在半导体芯片中的上半导体芯片的信号焊盘和封装衬底之间。 可以通过切断保险丝将测试垫转换成虚拟焊盘。