Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices
    1.
    发明授权
    Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices 有权
    形成具有自对准触点和低k间隔物的半导体器件的方法以及所得到的器件

    公开(公告)号:US08524592B1

    公开(公告)日:2013-09-03

    申请号:US13584055

    申请日:2012-08-13

    Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

    Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分,从而暴露牺牲栅电极的侧壁的至少一部分,并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中,该方法还包括在衬垫层之上形成牺牲间隙填充材料,暴露和去除牺牲栅极电极,从而限定由衬里层横向限定的栅极腔,形成替代栅极结构,去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件,其包括栅极覆盖层,位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层,以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

    Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation
    2.
    发明授权
    Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation 有权
    形成具有纳米线栅极结构的三维半导体器件的方法,其中在源极/漏极形成之后形成纳米线栅极结构

    公开(公告)号:US08541274B1

    公开(公告)日:2013-09-24

    申请号:US13609828

    申请日:2012-09-11

    Abstract: In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.

    Abstract translation: 在一个实例中,本文公开的方法包括形成由半导体材料构成的鳍片,其中鳍片具有第一成形截面构造,在鳍片之上形成牺牲栅极结构,形成邻近至少一部分的侧壁间隔物 的牺牲栅极结构,并且去除牺牲栅极结构,从而限定暴露鳍片的一部分的栅极腔。 该方法还包括以下步骤:在鳍的暴露部分上执行翅片回流处理以限定具有与第一截面构造不同的横截面构造的纳米线结构,并在栅腔中形成替代栅极结构 并且至少部分地围绕纳米线结构。

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