摘要:
In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.
摘要:
Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also include an interconnect using an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.
摘要:
Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.
摘要:
Embodiments of methods and apparatuses for multicast handling in mixed core systems have been described. A method for multicast handling in mixed core systems includes configuring broadcast group registers located in targets. The method also includes receiving a request to create a broadcast group and creating the broadcast group. Finally, the method includes transmitting the broadcast group to targets with broadcast group registers that correspond to the broadcast group.
摘要:
Various methods and apparatuses are described in which an interconnect couples to a plurality of initiator network resources and a plurality of target network resources. The interconnect may include a first stage of circuitry, a second stage of circuitry, and an arbitration controller. The first stage of circuitry receives incoming transactions from the plurality of initiator network resources. The second stage of circuitry passes outgoing transactions to the plurality of target network resources connecting to the interconnect. The arbitration controller arbitrates transactions from the plurality of initiator network resources destined to one or more of the target network resources. The target network resources supply their availability to service a transaction to the arbitration controller. The arbitration controller implements an arbitration policy that filters out transactions from the arbitration process those transactions from initiator network resources destine to target network resources that are currently not available to service a transaction.
摘要:
Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.
摘要:
Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area and power constraints in an electronic design system. The IP Generator receives a user-supplied file having data describing a configuration of an intellectual property (IP) design, the data includes one or more configuration parameters. The IP Generator further enables a transformation of the user-supplied file into a register transfer level design description. Next, the IP Generator receives user-supplied technology parameters and data-flow information. The technology parameters describe a configuration of the IP design. Next, the IP Generator executes a timing module based on the configuration of the IP design as well as executes a timing model for each hierarchical level in the IP design. The timing model predicts timing paths of a final logic circuit. Further, a result of the timing model is provided to the user prior to enabling a transformation of a register transfer level design into the simulation of a gate-level circuit design. Lastly, after the timing model has been executed, is the enablement of the transformation of the register transfer level design into the simulation of the gate-level circuit design.
摘要:
The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.