公开(公告)号：US5717895A

公开(公告)日：1998-02-10

申请号：US348056

申请日：1994-12-01

申请人： George W. Leedom ,  William T. Moore

发明人： George W. Leedom ,  William T. Moore

IPC分类号： G06F12/08

CPC分类号： G06F9/3013 ,  G06F12/0875 ,  G06F12/0888 ,  G06F9/30109 ,  G06F9/30138 ,  G06F9/3824

摘要： Method and apparatus for a scalar data cache in a scalar/vector supercomputer. The scalar data cache comprises a cache array and a cache controller. The cache array comprises a plurality of cache frames; each cache frame comprises a plurality of cache lines; and each cache line comprises a plurality of data words. The cache controller performs a broadside compare of the reference address against all addresses held in the cache, and translates the reference address into a cache-array address. For each cache line, there is a corresponding cache-line validity indication which is set "valid" only when every data word in the cache line contains valid data. A cache-line validity comparator operates to provide a cache-line-hit indication if a data word requested is in a valid cache line. A cache-load controller is described for loading data from a common memory into every data word of a cache line and for marking the cache line "valid". For at least one of the plurality of scalar registers, a cache accessor is described for providing fetch access to the data words in the cache array, and for providing write-through-cache capability to the data words in the cache array.

摘要翻译： 标量/向量超级计算机中的标量数据缓存的方法和装置。 标量数据高速缓存包括高速缓存阵列和高速缓存控制器。 高速缓存阵列包括多个缓存帧; 每个缓存帧包括多个高速缓存行; 并且每个高速缓存行包括多个数据字。 高速缓存控制器执行参考地址与保存在高速缓存中的所有地址的宽边比较，并将参考地址转换为高速缓存阵列地址。 对于每个高速缓存行，只有当高速缓存行中的每个数据字都包含有效数据时，才有一个对应的高速缓存线有效性指示被设置为“有效”。 如果请求的数据字在有效的高速缓存行中，则高速缓存行有效性比较器用于提供高速缓存行命中指示。 描述了缓存负载控制器，用于将数据从公共存储器加载到高速缓存行的每个数据字中，并用于标记高速缓存行“有效”。 对于多个标量寄存器中的至少一个，描述了高速缓存存取器，用于提供对高速缓存阵列中的数据字的取出访问，以及用于向缓存阵列中的数据字提供直写缓存能力。

公开(公告)号：US4924094A

公开(公告)日：1990-05-08

申请号：US27978

申请日：1987-03-19

申请人： William T. Moore

发明人： William T. Moore

IPC分类号： H04N5/33

CPC分类号： H04N5/33

摘要： Conventional scanners used in thermal imagers scan the image along curved lines rather than straight lines, resulting in image curvature in the display. The invention eliminates this by processing the video signal from the scanner to compose an output video signal which represents scanning along straight lines (18) across the image. The output signal is composed of a number of successive portions (A to F) each derived from a different line or lines of the video signal provided by the scanner.

摘要翻译： 热成像仪中使用的常规扫描仪沿着曲线而不是直线扫描图像，导致显示屏中的图像曲率。 本发明通过处理来自扫描仪的视频信号来消除这一点，以构成一个输出视频信号，该输出视频信号表示跨越图像的直线（18）的扫描。 输出信号由多个连续部分（A至F）组成，每个部分由扫描器提供的视频信号的不同行或行导出。

公开(公告)号：US4763192A

公开(公告)日：1988-08-09

申请号：US897855

申请日：1986-08-19

申请人： William T. Moore ,  Paul J. Robertson ,  Kenneth J. Wallace

发明人： William T. Moore ,  Paul J. Robertson ,  Kenneth J. Wallace

IPC分类号： H04N3/09 ,  H04N5/33 ,  H04N3/08

CPC分类号： H04N3/09

摘要： A twin polygon thermal imager is provided with a compensator for compensating for horizontal distortion in the image produced on a CRT. The distortion compensator applies an amount of correction which is determined, in each horizontal line, to compensate for the particular magnitude of the distortion in that line. The amount of correction needed is determined as a function of the angle between the rotational axis of the polygons and the particular facets thereof producing the particular video line. Compensation is achieved by adjusting the timing and the frequency at which digital video data is read-out from a signal store.

摘要翻译： 双面多面体热成像仪设置有用于补偿CRT上产生的图像中的水平失真的补偿器。 失真补偿器应用在每个水平线中确定的补偿量来补偿该行中的失真的特定幅度。 所需的校正量被确定为多边形的旋转轴线与其产生特定视频线的特定面之间的角度的函数。 通过调整从信号存储器读出数字视频数据的定时和频率来实现补偿。

公开(公告)号：US4752824A

公开(公告)日：1988-06-21

申请号：US28505

申请日：1987-03-20

申请人： William T. Moore

发明人： William T. Moore

IPC分类号： H04N5/33 ,  H04N7/18

CPC分类号： H04N5/33 ,  H04N7/183

摘要： Thermal imaging apparatus particularly but not exclusively for use on an aircraft with a head-up display is provided with signal processing means which progressively expands or compresses the image in the vertical and/or horizontal direction to compensate for parallax arising from the difference in the positions of the observer and the scanner. The adjustment is performed, in the preferred embodiment, as a function of height of the aircraft.

摘要翻译： 特别但不排他地用于具有平视显示器的飞行器的热成像装置设置有信号处理装置，其在垂直和/或水平方向上逐渐扩展或压缩图像以补偿由位置差异引起的视差 的观察者和扫描仪。 在优选实施例中，作为飞行器的高度的函数来执行调整。

公开(公告)号：US4202597A

公开(公告)日：1980-05-13

申请号：US865781

申请日：1977-12-30

申请人： William T. Moore

发明人： William T. Moore

IPC分类号： G02B26/12 ,  H04N3/09 ,  G02B27/17

CPC分类号： G02B26/126 ,  H04N3/09

摘要： In optical scanning systems loss in spatial resolution can result in coupling systems incorporating off axis concave mirrors by virtue of image rotation. In such systems compensation can be introduced for this image rotation by inclining the axis of oscillation of the scanning mirror at a small angle to the plane of that mirror.

摘要翻译： 在光学扫描系统中，通过图像旋转，空间分辨率的损失可能导致结合离轴凹面镜的系统。 在这种系统中，通过使扫描反射镜的振荡轴与该反射镜的平面成小角度倾斜，可以对该图像旋转引入补偿。

公开(公告)号：US4095502A

公开(公告)日：1978-06-20

申请号：US688824

申请日：1976-05-21

申请人： William T. Moore ,  Tadayaki Adachi

发明人： William T. Moore ,  Tadayaki Adachi

IPC分类号： G10H1/053 ,  G10H3/00

CPC分类号： G10H1/053

摘要： In an electronic musical instrument of the type having keys, a system for controlling the volume of the sound produced by the instrument when the keys are depressed or struck. For each key, the system comprises a tone generator, a gate coupled between the tone generator and the speaker of the instrument; and control means for producing a control signal having an amplitude which is a function of the speed at which its associated key is moved while being depressed. The control signal is applied to the gate to pass the output of the tone generator to the speaker and to control the volume of the sound produced by the speaker.

摘要翻译： 在具有按键的类型的电子乐器中，用于当琴键被按下或敲击时控制由乐器产生的声音的音量的系统。 对于每个键，系统包括音调发生器，耦合在乐音发生器和乐器扬声器之间的门; 以及控制装置，用于产生一个控制信号，该控制信号的幅度是其相关键在被按压时移动的速度的函数。 控制信号被施加到门以将音调发生器的输出传递到扬声器并且控制扬声器产生的声音的音量。

公开(公告)号：US07334110B1

公开(公告)日：2008-02-19

申请号：US10643586

申请日：2003-08-18

申请人： Gregory J. Faanes ,  Steven L. Scott ,  Eric P. Lundberg ,  William T. Moore, Jr. ,  Timothy J. Johnson

发明人： Gregory J. Faanes ,  Steven L. Scott ,  Eric P. Lundberg ,  William T. Moore, Jr. ,  Timothy J. Johnson

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867

摘要： In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method comprising sending a vector instruction from the scalar processing unit to the vector dispatch unit, wherein sending includes marking the vector instruction as complete if the vector instruction is not a vector memory instruction and if the vector instruction does not require scalar operands, reading a scalar operand, wherein reading includes transferring the scalar operand from the scalar processing unit to the vector dispatch unit, predispatching the vector instruction within the vector dispatch unit if the vector instruction is scalar committed, dispatching the predispatched vector instruction if all required operands are ready, and executing the dispatched vector instruction as a function of the scalar operand.

摘要翻译： 在具有标量处理单元和向量处理单元的计算机系统中，其中矢量处理单元包括矢量调度单元，将标量处理单元与矢量处理单元的操作分离的系统和方法，所述方法包括发送 从标量处理单元到矢量调度单元的向量指令，其中如果向量指令不是向量存储器指令，并且如果该向量指令不需要标量操作数，读取标量操作数，则发送包括将该向量指令标记为完成，其中， 读取包括将标量操作数从标量处理单元传送到向量调度单元，如果向量指令是标量提交的，则在向量调度单元内预分配向量指令，如果所有需要的操作数都准备就调度预分配向量指令，并执行调度 向量指令作为标量操作数的函数 。

公开(公告)号：US6012135A

公开(公告)日：2000-01-04

申请号：US347964

申请日：1994-12-01

申请人： George W Leedom ,  William T. Moore

发明人： George W Leedom ,  William T. Moore

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0292

摘要： Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a plurality of segment-register sets. Each segment-register set holds values which specify address boundaries and translation mapping of a corresponding logical segment. A segment detector is coupled to the plurality of segment-register sets, wherein the segment detector operates to determine whether the logical address is within the specified address boundaries of the logical segment. An address mapper is coupled to the plurality of segment-register sets, wherein the address mapper operates to translate the logical address into a physical address. A translation controller is connected to the segment detector and the address translator, wherein the translation controller operates to output the physical address if the segment detector determines that the logical address is within the specified address boundaries of the logical segment. One embodiment of the segment-register set includes a base address, a limit address, and a physical mapping bias. One embodiment of the computer includes a plurality of address ports, wherein each address port includes a logical address translator.

摘要翻译： 逻辑地址转换器的方法和装置，其将逻辑地址转换成计算机中的物理地址。 计算机包括多个地址端口。 每个地址端口包括逻辑地址转换器，其包括多个段寄存器集合。 每个段寄存器组保存指定相应逻辑段的地址边界和转换映射的值。 段检测器耦合到多个段寄存器集合，其中段检测器操作以确定逻辑地址是否在逻辑段的指定地址边界内。 地址映射器耦合到多个段寄存器集合，其中地址映射器操作以将逻辑地址转换为物理地址。 翻译控制器连接到段检测器和地址转换器，其中如果段检测器确定逻辑地址在逻辑段的指定地址边界内，则翻译控制器操作以输出物理地址。 段寄存器集合的一个实施例包括基地址，限制地址和物理映射偏置。 计算机的一个实施例包括多个地址端口，其中每个地址端口包括逻辑地址转换器。

公开(公告)号：US5349677A

公开(公告)日：1994-09-20

申请号：US683095

申请日：1991-04-10

申请人： Seymour R. Cray ,  James R. Bedell ,  Dennis W. Kuba ,  William T. Moore, Jr.

发明人： Seymour R. Cray ,  James R. Bedell ,  Dennis W. Kuba ,  William T. Moore, Jr.

IPC分类号： G06F17/16 ,  G06F9/312 ,  G06F15/76 ,  G06F15/78 ,  G06F9/34

CPC分类号： G06F15/8076

摘要： Improved performance is obtained in computers of the type having vector registers which communicate with one or more functional units and common memory. As elements of a vector are read from a vector register for transmission to common memory or as operands to a functional unit, the vector register immediately becomes available to receive and store elements of a vector from common memory or a functional unit. The element-by-element storing takes place simultaneously with the element-by-element reading, and trails the reading by at least one element so as to not overwrite elements yet to be read. Through the use of this technique a vector register can be loaded with a vector for a subsequent operation without having to wait for the completion of the previous operation which uses the same vector register.

摘要翻译： 在具有与一个或多个功能单元和公共存储器通信的向量寄存器的类型的计算机中获得了改进的性能。 由向量寄存器读取向量寄存器中的元素，以传输到公共存储器或作为功能单元的操作数，向量寄存器立即可用于从公共存储器或功能单元接收和存储向量的元素。 逐个元件存储与逐个元素读取同时发生，并且通过至少一个元素追踪读取，以便不覆盖尚未被读取的元素。 通过使用这种技术，向量寄存器可以加载一个向量，用于后续操作，而不必等待使用相同向量寄存器的先前操作的完成。

公开(公告)号：US5211565A

公开(公告)日：1993-05-18

申请号：US854312

申请日：1992-03-19

申请人： Nicholas J. Krajewski ,  Carl D. Breske ,  David J. Johnson ,  David R. Kiefer ,  Kent T. McDaniel ,  William T. Moore, Jr. ,  Michael R. Edwards ,  Bricky A. Stephenson ,  Anthony A. Vacca

发明人： Nicholas J. Krajewski ,  Carl D. Breske ,  David J. Johnson ,  David R. Kiefer ,  Kent T. McDaniel ,  William T. Moore, Jr. ,  Michael R. Edwards ,  Bricky A. Stephenson ,  Anthony A. Vacca

IPC分类号： H01R4/01 ,  H01R12/50 ,  H01R12/71 ,  H01R12/79 ,  H01R12/82 ,  H05K1/14 ,  H05K3/32 ,  H05K3/40 ,  H05K7/14

CPC分类号： H01R12/71 ,  H01R12/79 ,  H01R12/82 ,  H01R23/68 ,  H01R4/01 ,  H05K7/1444 ,  H05K1/14 ,  H05K1/145 ,  H05K3/325 ,  H05K3/403

摘要： The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.

摘要翻译： 本发明包括多个层叠的平面处理电路板，其由至少一侧由基本上垂直于平面处理板定位的多个存储器板，由正交互连模块连接的处理器和存储器板包围。 正交互连模块允许处理板与存储板的紧密间隔的正交连接。 存储器板具有密集封装的设计，其具有位于存储器板上的多个可移除的存储芯片堆叠。