公开(公告)号：US20100289467A1

公开(公告)日：2010-11-18

申请号：US12578666

申请日：2009-10-14

Applicant: Chung-Wen WU ,  Chien-Cheng Tu ,  Wen-Hsuan Lin

Inventor： Chung-Wen WU ,  Chien-Cheng Tu ,  Wen-Hsuan Lin

IPC: G05F1/10

CPC classification number: H02M3/33523 ,  H02M2001/0032 ,  Y02B70/16

Abstract: In a normal mode, the power supply is fed back in a close loop, but in a power saving mode, the power supply is fed back in an open loop. When it is detected that the power supply is continuously fed back in the open loop and in a substantially zero output status, the power supply circuit enters a power down status. If the back-stage circuit needs power supply again, then the feedback is switched to the close loop and the power supply circuit enters the normal mode.

Abstract translation: 在正常模式下，电源以闭环反馈，但在省电模式下，电源以开环反馈。 当检测到电源在开环中连续反馈并且基本为零输出状态时，电源电路进入断电状态。 如果后级电路需要再次供电，则反馈被切换到闭环，电源电路进入正常模式。

公开(公告)号：US07589795B2

公开(公告)日：2009-09-15

申请号：US11308424

申请日：2006-03-23

Applicant: Chung-Wen Wu ,  Wen-Hsuan Lin

Inventor： Chung-Wen Wu ,  Wen-Hsuan Lin

IPC: H04N5/18 ,  H03M1/12

CPC classification number: H03M1/1295 ,  H03M1/1023 ,  H04N5/18

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract translation: 提供了一个自动钳位模数转换器（A / D转换器），它包括A / D转换器，开关，比较器，双向计数器和数模转换器（D / A转换器） 。 其中，A / D转换器从节点接收模拟信号，然后根据DC偏置电平将模拟信号转换为数字信号。 开关耦合在节点和固定电压电平之间，并根据钳位信号导通或关断。 比较器根据数字信号和偏移值之间的比较结果输出比较信号。 双向计数器输出计数，根据比较信号增加或减少计数。 D / A转换器将计数转换为DC偏移电平，并向A / D转换器提供DC偏移电平。

公开(公告)号：US20070182856A1

公开(公告)日：2007-08-09

申请号：US11308424

申请日：2006-03-23

Applicant: Chung-Wen Wu ,  Wen-Hsuan Lin

Inventor： Chung-Wen Wu ,  Wen-Hsuan Lin

IPC: H03M1/12 ,  H04N5/18

CPC classification number: H03M1/1295 ,  H03M1/1023 ,  H04N5/18

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract translation: 提供了一个自动钳位模数转换器（A / D转换器），它包括A / D转换器，开关，比较器，双向计数器和数模转换器（D / A转换器） 。 其中，A / D转换器从节点接收模拟信号，然后根据DC偏置电平将模拟信号转换为数字信号。 开关耦合在节点和固定电压电平之间，并根据钳位信号导通或关断。 比较器根据数字信号和偏移值之间的比较结果输出比较信号。 双向计数器输出计数，根据比较信号增加或减少计数。 D / A转换器将计数转换为DC偏移电平，并向A / D转换器提供DC偏移电平。

公开(公告)号：US08384640B2

公开(公告)日：2013-02-26

申请号：US11762039

申请日：2007-06-12

Applicant: Chung-Wen Wu ,  Min-Jung Chen ,  Wen-Hsuan Lin

Inventor： Chung-Wen Wu ,  Min-Jung Chen ,  Wen-Hsuan Lin

IPC: G06K9/40

CPC classification number: G09G3/3648 ,  G09G5/18 ,  G09G2310/061 ,  G09G2320/0252 ,  G09G2360/18

Abstract: An image processing method for a display device, for enhancing image quality, includes receiving video signals, sequentially generating a plurality of image data according to the video signals, and sequentially displaying the plurality of image data on a panel of the display device. Each of the plurality of image data includes a frame data and a low-gray-level frame data respectively corresponding to a frame output duration and a vertical blanking duration in a timing sequence of the video signals.

Abstract translation: 一种用于提高图像质量的显示装置的图像处理方法，包括接收视频信号，根据视频信号顺序生成多个图像数据，并在显示装置的面板上顺序显示多个图像数据。 多个图像数据中的每一个包括分别对应于视频信号的定时序列中的帧输出持续时间和垂直消隐持续时间的帧数据和低灰度级帧数据。

公开(公告)号：US20080263264A1

公开(公告)日：2008-10-23

申请号：US11762083

申请日：2007-06-13

Applicant: Wen-Hsuan Lin ,  Kuo-Wei Huang

Inventor： Wen-Hsuan Lin ,  Kuo-Wei Huang

IPC: G06F12/00

CPC classification number: G06F12/0238 ,  G06F12/0246

Abstract: A data access control system of a memory includes a micro-processor, having a micro-controller, a command decoder, and a memory interface. The data access control system can be used to control display driving of a display system. The command decoder is used to decode the content of a data access command. A memory unit is configured into a first region for storing a first-type data being stored in a memory manner, and a second region for storing a second-type data being stored in a simulation manner of the memory. A bus is connected between the micro-processor and the memory unit, for performing data transmission. The micro-processor uses the memory interface to write data into the first region of the memory unit, and uses the command decoder to convert the nonvolatile data and write into the second region of the memory unit.

Abstract translation: 存储器的数据访问控制系统包括具有微控制器，命令解码器和存储器接口的微处理器。 数据访问控制系统可用于控制显示系统的显示驱动。 命令解码器用于对数据访问命令的内容进行解码。 存储单元被配置为用于存储以存储方式存储的第一类型数据的第一区域和用于存储以存储器的模拟方式存储的第二类型数据的第二区域。 总线连接在微处理器和存储器单元之间，用于执行数据传输。 微处理器使用存储器接口将数据写入存储器单元的第一区域，并使用命令解码器来转换非易失性数据并写入存储器单元的第二区域。

公开(公告)号：US20090254688A1

公开(公告)日：2009-10-08

申请号：US12127793

申请日：2008-05-27

Applicant: Wen-Hsuan Lin ,  Chun-Liang Chen

Inventor： Wen-Hsuan Lin ,  Chun-Liang Chen

IPC: G06F13/18

CPC classification number: G06F13/1663

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract translation: 为了降低生产成本，本发明提供了一种用于LCD控制器的微处理器装置，其包括存储器，第一处理单元，第二处理单元，第一仲裁器和第二仲裁器。 存储器用于存储数据。 第一处理单元用于执行第一程序。 第二处理单元用于执行第二程序。 第一仲裁器耦合到第一处理单元和第二处理单元，用于确定第一处理单元和第二处理单元的操作顺序。 第二仲裁器耦合到第一处理单元，第二处理单元和存储器，并用于确定第一处理单元和第二处理单元的存储器存取顺序。

公开(公告)号：US20120206579A1

公开(公告)日：2012-08-16

申请号：US13089335

申请日：2011-04-19

Applicant: Chung-Wen Wu ,  Wen-Hsuan Lin ,  Chia-Chun Liu ,  Sih-Ting Wang

Inventor： Chung-Wen Wu ,  Wen-Hsuan Lin ,  Chia-Chun Liu ,  Sih-Ting Wang

IPC: H04N13/04

CPC classification number: H04N13/398 ,  G09G3/003 ,  G09G3/3406 ,  G09G2320/0209 ,  H04N13/341

Abstract: A three-dimensional (3D) video processing device capable of avoiding crosstalk between adjacent frames includes a video processing circuit and a control circuit. The video processing circuit is configured to generate a 3D video signal having a first frame timing. The 3D video signal is used to control a panel to update, to thereby display 3D video frames in accordance with a second frame timing which is a delayed version of the first frame timing. The control circuit is utilized for generating a backlight control signal. A switching timing of the backlight control signal is determined according to the second frame timing.

Abstract translation: 能够避免相邻帧之间的串扰的三维（3D）视频处理装置包括视频处理电路和控制电路。 视频处理电路被配置为生成具有第一帧定时的3D视频信号。 3D视频信号用于控制面板更新，从而根据作为第一帧定时的延迟版本的第二帧定时显示3D视频帧。 控制电路用于产生背光控制信号。 根据第二帧定时确定背光控制信号的切换定时。

公开(公告)号：US07725634B2

公开(公告)日：2010-05-25

申请号：US12127793

申请日：2008-05-27

Applicant: Wen-Hsuan Lin ,  Chun-Liang Chen

Inventor： Wen-Hsuan Lin ,  Chun-Liang Chen

IPC: G06F13/00

CPC classification number: G06F13/1663

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract translation: 为了降低生产成本，本发明提供了一种用于LCD控制器的微处理器装置，其包括存储器，第一处理单元，第二处理单元，第一仲裁器和第二仲裁器。 存储器用于存储数据。 第一处理单元用于执行第一程序。 第二处理单元用于执行第二程序。 第一仲裁器耦合到第一处理单元和第二处理单元，用于确定第一处理单元和第二处理单元的操作顺序。 第二仲裁器耦合到第一处理单元，第二处理单元和存储器，并用于确定第一处理单元和第二处理单元的存储器存取顺序。

公开(公告)号：US20070182852A1

公开(公告)日：2007-08-09

申请号：US11308480

申请日：2006-03-29

Applicant: Chung-Wen Wu ,  Wen-Hsuan Lin

Inventor： Chung-Wen Wu ,  Wen-Hsuan Lin

IPC: H04N5/04

CPC classification number: H04N7/012

Abstract: A method and an apparatus for interlace scanning video signal frequency multiplication are provided. The method includes the following steps: first, removing a part of a first vertical synchronous signal (V-sync signal) which is asynchronous with a first horizontal synchronous signal (H-sync signal); next, capturing a first field and a second field from an interlace scan video signal according to the first V-sync signal obtained in the previous step; performing a frequency multiplication on a frame made up by the first and second fields, and producing a second V-sync signal and a second H-sync signal; finally, compensating for the second V-sync signal on a border between two fields of the frame after the frequency multiplication according to the second H-sync signal. Thereby, the method can be used to perform frequency multiplication using a line buffer instead of a frame buffer, to output through interface scanning without sacrificing image quality.

Abstract translation: 提供了隔行扫描视频信号倍频的方法和装置。 该方法包括以下步骤：首先去除与第一水平同步信号（H同步信号）异步的第一垂直同步信号（V-sync信号）的一部分; 接下来，根据在前一步骤中获得的第一V-sync信号从隔行扫描视频信号捕获第一场和第二场; 对由第一和第二场组成的帧执行倍频，并产生第二V同步信号和第二H同步信号; 最后，根据第二H同步信号在倍频之后的帧的两个场之间的边界上补偿第二V同步信号。 因此，该方法可以用于使用行缓冲器而不是帧缓冲器进行倍频，以通过接口扫描输出而不牺牲图像质量。

公开(公告)号：US08582328B2

公开(公告)日：2013-11-12

申请号：US12578666

申请日：2009-10-14

Applicant: Chung-Wen Wu ,  Chien-Cheng Tu ,  Wen-Hsuan Lin

Inventor： Chung-Wen Wu ,  Chien-Cheng Tu ,  Wen-Hsuan Lin

IPC: H02M3/335

CPC classification number: H02M3/33523 ,  H02M2001/0032 ,  Y02B70/16

Abstract: In a normal mode, the power supply is fed back in a close loop, but in a power saving mode, the power supply is fed back in an open loop. When it is detected that the power supply is continuously fed back in the open loop and in a substantially zero output status, the power supply circuit enters a power down status. If the back-stage circuit needs power supply again, then the feedback is switched to the close loop and the power supply circuit enters the normal mode.

Abstract translation: 在正常模式下，电源以闭环反馈，但在省电模式下，电源以开环反馈。 当检测到电源在开环中连续反馈并且基本为零输出状态时，电源电路进入断电状态。 如果后级电路需要再次供电，则反馈被切换到闭环，电源电路进入正常模式。