知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.016 seconds)

    Techniques for providing clock signals in clock networks
    1.
    发明授权
    Techniques for providing clock signals in clock networks 有权
    在时钟网络中提供时钟信号的技术

    公开(公告)号：US08581653B1

    公开(公告)日：2013-11-12

    申请号：US13328784

    申请日：2011-12-16

    Applicant: Victor Maruri ,  Arch Zaliznyak ,  Ramanand Venkata ,  Henry Y. Lui

    Inventor： Victor Maruri ,  Arch Zaliznyak ,  Ramanand Venkata ,  Henry Y. Lui

    IPC: G06F1/04 ,  H03K3/00

    CPC classification number: G06F1/10

    Abstract: An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.

    Abstract translation: 集成电路包括可操作以提供第一时钟信号的本地时钟网络和耦合以从本地时钟网络接收第一时钟信号的接口电路。 接口电路可操作以基于第一时钟信号产生第二时钟信号。 时钟线耦合到接口电路。 时钟线具有固定长度。 第二时钟信号通过时钟线提供给多路复用器电路。 多路复用器电路基于第二时钟信号提供第三时钟信号。 另一个时钟网络被耦合以从多路复用器电路接收第三时钟信号。

    Integrated circuits with clock selection circuitry
    6.
    发明授权
    Integrated circuits with clock selection circuitry 有权
    具有时钟选择电路的集成电路

    公开(公告)号：US09515880B1

    公开(公告)日：2016-12-06

    申请号：US13338898

    申请日：2011-12-28

    Applicant: Ramanand Venkata ,  Henry Y. Lui ,  Victor Maruri ,  David W. Mendel ,  Andrew Bellis

    Inventor： Ramanand Venkata ,  Henry Y. Lui ,  Victor Maruri ,  David W. Mendel ,  Andrew Bellis

    IPC: G06F15/177 ,  G06F1/00 ,  G06F1/04 ,  G06F15/16 ,  H04L12/24 ,  G06F1/10 ,  G06F17/50 ,  G06F9/445

    CPC classification number: H04L41/0816 ,  G06F1/04 ,  G06F1/10 ,  G06F9/44505 ,  G06F17/5054 ,  H04J3/0688 ,  H04J3/0691 ,  H04J3/0697 ,  H04L41/0813

    Abstract: An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.

    Abstract translation: 集成电路设备可以包括可以动态地重新配置以执行不同的任务的处理电路，每个任务利用不同的系统时钟资源。 该装置可以包括时钟选择电路，其可以选择性地将期望的时钟信号路由到相应的处理电路。 可以基于该处理电路的当前配置来选择提供给每个处理电路的时钟信号。 网络交换机中的客户端处理电路可以耦合到可互换的客户端网络。 可以基于当前耦合到网络交换机的客户端网络的特性来动态地重新配置客户端处理电路。 通过动态地选择哪些时钟资源被提供给处理电路，诸如相对稀少的全局时钟信号的时钟资源可以被保留用于只能用相对稀少的时钟资源起作用的处理电路。 以这种方式安排，可以不断优化时钟资源利用。

    Interconnection resources for programmable logic integrated circuit devices
    9.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US06366120B1

    公开(公告)日：2002-04-02

    申请号：US09517146

    申请日：2000-03-02

    Applicant: James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    Inventor： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC: H03K190177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

Patent Agency Ranking