公开(公告)号：US20110195530A1

公开(公告)日：2011-08-11

申请号：US12982032

申请日：2010-12-30

Applicant: Masachika Masuda ,  Toshihiko Usami

Inventor： Masachika Masuda ,  Toshihiko Usami

IPC: H01L21/66

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  G06K19/077 ,  G06K19/07732 ,  G11C5/02 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5388 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/074 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.

Abstract translation: 一种包括形成中间产品的方法，所述中间产品被配置为包括布线基板，所述布线基板包括多个第一电极，多个第二电极和多个测试电极，第一半导体芯片安装在所述布线基板上并且包括多个 分别与第一电极电连接的第一焊盘和堆叠在第一半导体芯片上并包括分别电连接到第二电极的多个第二焊盘的第二半导体芯片; 封装第一和第二半导体芯片; 以及在封装了第一和第二半导体芯片之后，通过使用测试电极对第一和第二半导体芯片进行电测试。

公开(公告)号：US08502395B2

公开(公告)日：2013-08-06

申请号：US13413914

申请日：2012-03-07

Applicant: Masachika Masuda ,  Toshihiko Usami

Inventor： Masachika Masuda ,  Toshihiko Usami

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  G06K19/077 ,  G06K19/07732 ,  G11C5/02 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5388 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/074 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.

Abstract translation: 一种半导体器件，其特征在于具有由第一边缘和相对的第二边缘限定的第一表面的基板，形成在第一表面上的电极焊盘，安装在第一边缘和电极焊盘之间的第一表面上的第一半导体芯片， 每个电连接到对应的电极焊盘，堆叠在第一半导体芯片上的第二半导体芯片，并且包括每个电连接到相应的电极焊盘的第二焊盘;第三半导体芯片，安装在第二边缘和第二半导体衬底之间的衬底的第一表面上 电极焊盘，并且包括每个电连接到相应的电极焊盘的第三焊盘，其中一个电极焊盘电连接到一个第一焊盘，一个第二焊盘和一个第三焊盘，另一个电极焊盘电连接到第一焊盘和第二焊盘 通过单独的接合线。

公开(公告)号：US20120211875A1

公开(公告)日：2012-08-23

申请号：US13462499

申请日：2012-05-02

Applicant: Toshihiko USAMI

Inventor： Toshihiko USAMI

IPC: H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.

Abstract translation: 半导体器件包括第一至第三半导体芯片。 第二半导体芯片堆叠在第一半导体芯片上。 第三半导体芯片堆叠在第二半导体芯片上。 第二半导体芯片屏蔽第一半导体芯片免受由第三半导体芯片产生的噪声。 第二半导体芯片屏蔽第三半导体芯片免受由第一半导体芯片产生的噪声。

公开(公告)号：US08159062B2

公开(公告)日：2012-04-17

申请号：US13243583

申请日：2011-09-23

Applicant: Masachika Masuda ,  Toshihiko Usami

Inventor： Masachika Masuda ,  Toshihiko Usami

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  G06K19/077 ,  G06K19/07732 ,  G11C5/02 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5388 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/074 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.

Abstract translation: 一种包括形成中间产品的方法，所述中间产品被配置为包括布线基板，所述布线基板包括多个第一电极，多个第二电极和多个测试电极，第一半导体芯片安装在所述布线基板上并且包括多个 分别与第一电极电连接的第一焊盘和堆叠在第一半导体芯片上并包括分别电连接到第二电极的多个第二焊盘的第二半导体芯片; 封装第一和第二半导体芯片; 以及在封装了第一和第二半导体芯片之后，通过使用测试电极对第一和第二半导体芯片进行电测试。

公开(公告)号：US07989134B2

公开(公告)日：2011-08-02

申请号：US12019112

申请日：2008-01-24

Applicant: Toshihiko Usami ,  Masashi Miyakawa

Inventor： Toshihiko Usami ,  Masashi Miyakawa

IPC: G03G5/00

CPC classification number: G03G9/0806 ,  G03G9/0825 ,  G03G9/0827 ,  G03G9/08755

Abstract: To provide a toner manufacturing method including: dissolving or dispersing a toner material into an organic solvent to prepare a toner solution, the toner material containing at least an active hydrogen group-containing compound, polymer reactive with the active hydrogen group-containing compound, binder resin, releasing agent and coloring agent; emulsifying or dispersing the toner solution into an aqueous medium to prepare an emulsified dispersion; reacting the active hydrogen group-containing compound with the polymer reactive with the active hydrogen group-containing compound in the aqueous medium produce an adhesive base material in the form of particle; and removing the organic solvent, wherein time X (hour) from a point where the organic solvent starts to be removed to a point where the concentration of the organic solvent reaches less than 12% by mass and temperature T (° C.) of the emulsified dispersion at the time X satisfy the relationship 5{exp(−0.2X)+1}≦T≦50X−0.2.

Abstract translation: 提供一种调色剂制造方法，包括：将调色剂材料溶解或分散到有机溶剂中以制备调色剂溶液，所述调色剂材料至少含有含活性氢基团的化合物，与含活性氢基团的化合物反应的聚合物，粘合剂 树脂，脱模剂和着色剂; 将调色剂溶液乳化或分散到水性介质中以制备乳化分散体; 使含活性氢基团的化合物与在水性介质中与含活性氢基团的化合物反应的聚合物反应，生成颗粒形式的粘合剂基材; 并除去有机溶剂开始被除去的时刻X（小时）到有机溶剂的浓度达到12质量％以下的时间和温度T（℃）的有机溶剂， 乳化分散体在时间X满足关系5 {exp（-0.2X）+1}＆nlE; T＆nlE; 50X-0.2。

公开(公告)号：US07879647B2

公开(公告)日：2011-02-01

申请号：US12574184

申请日：2009-10-06

Applicant: Masachika Masuda ,  Toshihiko Usami

Inventor： Masachika Masuda ,  Toshihiko Usami

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  G06K19/077 ,  G06K19/07732 ,  G11C5/02 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5388 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/074 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A technique for mounting two semiconductor chips over a wiring substrate including mounting a first chip having first bonding pads over a surface of the wiring substrate having electrodes and stacking the second chip having second bonding pads over the first chip; connecting each of the first bonding pads to an associated one of the electrodes of the wiring substrate via an associated first wire; and connecting each of the second bonding pads to an associated one of the electrodes of the wiring substrate via an associated second wire. The bondings being carried out using a reverse bonding method in which at least one of the first and second wires are first bonded to an associated one of the electrodes of the wiring substrate followed by the bonding thereof to an associated one of the bonding pads of the first or second semiconductor chip.

Abstract translation: 一种用于在布线基板上安装两个半导体芯片的技术，包括：在具有电极的布线基板的表面上安装具有第一焊盘的第一芯片，并将具有第二焊盘的第二芯片堆叠在第一芯片上; 通过相关联的第一线将每个第一接合焊盘连接到布线基板的相关联的一个电极; 以及通过相关联的第二线将每个第二接合焊盘连接到布线基板的相关联的一个电极。 使用反向接合方法进行接合，其中第一和第二线中的至少一个首先接合到布线基板的相关联的一个电极，然后将其接合到相关联的一个接合焊盘 第一或第二半导体芯片。

公开(公告)号：US20100213585A1

公开(公告)日：2010-08-26

申请号：US12693921

申请日：2010-01-26

Applicant: Toshihiko USAMI

Inventor： Toshihiko USAMI

IPC: H01L23/556

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.

Abstract translation: 半导体器件包括第一至第三半导体芯片。 第二半导体芯片堆叠在第一半导体芯片上。 第三半导体芯片堆叠在第二半导体芯片上。 第二半导体芯片屏蔽第一半导体芯片免受由第三半导体芯片产生的噪声。 第二半导体芯片屏蔽第三半导体芯片免受由第一半导体芯片产生的噪声。

公开(公告)号：US20100068850A1

公开(公告)日：2010-03-18

申请号：US12574184

申请日：2009-10-06

Applicant: Masachika Masuda ,  Toshihiko Usami

Inventor： Masachika Masuda ,  Toshihiko Usami

IPC: H01L21/98

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  G06K19/077 ,  G06K19/07732 ,  G11C5/02 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5388 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/074 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A technique for mounting two semiconductor chips over a wiring substrate including mounting a first chip having first bonding pads over a surface of the wiring substrate having electrodes and stacking the second chip having second bonding pads over the first chip; connecting each of the first bonding pads to an associated one of the electrodes of the wiring substrate via an associated first wire; and connecting each of the second bonding pads to an associated one of the electrodes of the wiring substrate via an associated second wire. The bondings being carried out using a reverse bonding method in which at least one of the first and second wires are first bonded to an associated one of the electrodes of the wiring substrate followed by the bonding thereof to an associated one of the bonding pads of the first or second semiconductor chip.

Abstract translation: 一种用于在布线基板上安装两个半导体芯片的技术，包括：在具有电极的布线基板的表面上安装具有第一焊盘的第一芯片，并将具有第二焊盘的第二芯片堆叠在第一芯片上; 通过相关联的第一线将每个第一接合焊盘连接到布线基板的相关联的一个电极; 以及通过相关联的第二线将每个第二接合焊盘连接到布线基板的相关联的一个电极。 使用反向接合方法进行接合，其中第一和第二线中的至少一个首先接合到布线基板的相关联的一个电极，然后将其接合到相关联的一个接合焊盘 第一或第二半导体芯片。

公开(公告)号：US20080182186A1

公开(公告)日：2008-07-31

申请号：US12019112

申请日：2008-01-24

Applicant: Toshihiko USAMI ,  Masashi MIYAKAWA

Inventor： Toshihiko USAMI ,  Masashi MIYAKAWA

IPC: G03G9/12 ,  G03G13/14

CPC classification number: G03G9/0806 ,  G03G9/0825 ,  G03G9/0827 ,  G03G9/08755

Abstract: To provide a toner manufacturing method including: dissolving or dispersing a toner material into an organic solvent to prepare a toner solution, the toner material containing at least an active hydrogen group-containing compound, polymer reactive with the active hydrogen group-containing compound, binder resin, releasing agent and coloring agent; emulsifying or dispersing the toner solution into an aqueous medium to prepare an emulsified dispersion; reacting the active hydrogen group-containing compound with the polymer reactive with the active hydrogen group-containing compound in the aqueous medium produce an adhesive base material in the form of particle; and removing the organic solvent, wherein time X (hour) from a point where the organic solvent starts to be removed to a point where the concentration of the organic solvent reaches less than 12% by mass and temperature T (° C.) of the emulsified dispersion at the time X satisfy the relationship 5{exp(−0.2 X)+1}≦T≦50 X−0.2.

Abstract translation: 提供一种调色剂制造方法，包括：将调色剂材料溶解或分散到有机溶剂中以制备调色剂溶液，所述调色剂材料至少含有含活性氢基团的化合物，与含活性氢基团的化合物反应的聚合物，粘合剂 树脂，脱模剂和着色剂; 将调色剂溶液乳化或分散到水性介质中以制备乳化分散体; 使含活性氢基团的化合物与在水性介质中与含活性氢基团的化合物反应的聚合物反应，生成颗粒形式的粘合剂基材; 并除去有机溶剂开始被除去的时刻X（小时）到有机溶剂的浓度达到12质量％以下的时间和温度T（℃）的有机溶剂， 乳化分散体在时间X满足关系5 {exp（-0.2 X）+1} <= T <= 50 X -0.2 。

公开(公告)号：US07061105B2

公开(公告)日：2006-06-13

申请号：US10743882

申请日：2003-12-24

Applicant: Masachika Masuda ,  Toshihiko Usami

Inventor： Masachika Masuda ,  Toshihiko Usami

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  G06K19/077 ,  G06K19/07732 ,  G11C5/02 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5388 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/074 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.