公开(公告)号：US20140032622A1

公开(公告)日：2014-01-30

申请号：US13560631

申请日：2012-07-27

申请人： Tony S. El-Kik

发明人： Tony S. El-Kik

IPC分类号： G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width.

摘要翻译： 执行数字分割的方法包括右移分配器以提供临时分配器，从暂时分红中减去临时分配器以提供差异，基于分红和差异中的至少一个来确定临时股利， 基于差异来转移商。 提供了相应的计算机可读介质和设备。 执行数字分割的系统包括计数器和除法电路。 计数器提供计数，分割电路可操作地耦合到计数器。 除法电路将除数除以分频器，以响应于计数器提供商。 计数器和除法电路中的至少一个被配置为接受具有可配置位宽的计数，除数，除法器和商中的至少一个。

公开(公告)号：US20100019799A1

公开(公告)日：2010-01-28

申请号：US12178286

申请日：2008-07-23

申请人： Tony S. El-Kik

发明人： Tony S. El-Kik

IPC分类号： G01R29/00 ,  H03L7/06

CPC分类号： H03L7/089 ,  G01R25/005 ,  H03L7/10

摘要： Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector comprises a first logic circuit for (i) sampling the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, and (ii) generating one or more error signals indicating a phase difference between the clock signal and the reference signal; and a second logic circuit for (i) sampling the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and (ii) generating one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal, wherein the error signal is generated on positive and negative edges of one or more of the clock signal and the reference signal; and applying the error signal to an oscillator to produce the clock signal.

摘要翻译： 为数字相位检测提供了改进频率锁定的方法和装置。 公开了一种用于评估时钟信号和参考信号之间的相位差的相位检测器。 所公开的相位检测器包括第一逻辑电路，用于（i）在时钟信号和参考信号中的一个或多个的正边沿对时钟信号和参考信号进行采样，以及（ii）产生指示相位的一个或多个误差信号 时钟信号与参考信号之间的差异; 以及第二逻辑电路，用于（i）在所述时钟信号和所述参考信号中的一个或多个的负沿上对所述时钟信号和所述参考信号进行采样，以及（ii）产生指示所述时钟信号和所述参考信号之间的相位差的一个或多个误差信号 信号和参考信号。 可以通过产生指示时钟信号和参考信号之间的相位差的误差信号来产生与参考信号相位对准的时钟信号，其中误差信号在一个或多个时钟的正和负边沿产生 信号和参考信号; 并将误差信号施加到振荡器以产生时钟信号。

公开(公告)号：US07342983B2

公开(公告)日：2008-03-11

申请号：US10785682

申请日：2004-02-24

申请人： Tony S. El-Kik

发明人： Tony S. El-Kik

IPC分类号： H04B1/10

CPC分类号： H03K5/1252

摘要： A digital filtering apparatus and method for digitally filtering out undesirable or invalid data from data signal lines. The digital filtering apparatus includes a digital delay element having one or more outputs, a comparator connected to the outputs of the digital delay element, and a final stage connected to the output of the comparator and the outputs of the digital delay element. The digital filtering apparatus recognizes and filters out invalid data from data received by the digital delay element, and allows valid data to pass through the filter. Data is considered invalid data if its logical data state transition has a duration less than the clock setting of the digital filtering apparatus. The clock setting can be established by the number of active delay components in the digital delay element. The inventive digital filtering apparatus represents an improvement over conventional analog filters, e.g., in manufacturing efficiency and filtering performance.

摘要翻译： 一种用于从数据信号线数字滤波不期望或无效数据的数字滤波装置和方法。 数字滤波装置包括具有一个或多个输出的数字延迟元件，连接到数字延迟元件的输出的比较器，以及连接到比较器的输出端和数字延迟元件的输出端的最后级。 数字滤波装置从数字延迟元件接收的数据识别并滤除无效数据，并允许有效数据通过滤波器。 如果其逻辑数据状态转换的持续时间小于数字滤波装置的时钟设置，则将数据视为无效数据。 时钟设置可以通过数字延迟元件中的有效延迟分量的数量来建立。 本发明的数字滤波装置代表了传统模拟滤波器的改进，例如在制造效率和滤波性能方面。

公开(公告)号：US07231467B2

公开(公告)日：2007-06-12

申请号：US10715746

申请日：2003-11-17

申请人： Thomas E. Baker ,  Laurence Edward Bays ,  Tony S. El-Kik

发明人： Thomas E. Baker ,  Laurence Edward Bays ,  Tony S. El-Kik

IPC分类号： G06F3/00

CPC分类号： G06F13/423

摘要： A method and apparatus implementing an enhanced protocol between an I2C master and an I2C slave. In various embodiments the invention permits greater addressability space and high priority access to the slave device. The enhanced protocol is implemented by the addition of command code data being transmitted which is recognized through an interface circuit inside the slave device. The invention provides an I2C solution for accessing high priority address space with one command byte, medium priority space with two command bytes and low priority space with three command bytes.

摘要翻译： 实现I2C主机和I2C从机之间的增强协议的方法和装置。 在各种实施例中，本发明允许更大的可寻址空间和对从属设备的高优先级访问。 增强协议通过添加被发送的命令码数据来实现，该数据通过从设备内部的接口电路被识别。 本发明提供了一种I2C解决方案，用于通过一个命令字节访问高优先级地址空间，具有两个命令字节的中等优先级空间和三个命令字节的低优先级空间。

公开(公告)号：US20130321043A1

公开(公告)日：2013-12-05

申请号：US13485982

申请日：2012-06-01

申请人： Tony S. El-Kik

发明人： Tony S. El-Kik

IPC分类号： H03L7/00

CPC分类号： G06F1/12

摘要： A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

摘要翻译： 脉冲同步器电路将源 - 时钟域下生成的输入数据信号转换成目的时钟域下的输出数据信号，其中目的时钟独立于源时钟。 当源时钟比目的地时钟慢，当源时钟比目的地时钟慢时，脉冲同步器电路成功地将输入数据信号中的每个数据脉冲转换成输出数据信号中的相应数据脉冲，当输入数据 脉冲具有一个源时钟周期的持续时间，并且当输入数据脉冲具有多个源时钟周期的持续时间时。 脉冲同步器电路具有源极域电路和目标域电路。 源域电路检测输入数据脉冲，并确定它们是单周期还是多周期数据脉冲。 目标域电路基于源域电路的处理产生输出数据脉冲。

公开(公告)号：US20080013663A1

公开(公告)日：2008-01-17

申请号：US11601998

申请日：2006-11-20

申请人： William P. Cornelius ,  Tony S. El-Kik ,  Stephen A. Masnica ,  Parag Parikh ,  Anthony W. Seaman

发明人： William P. Cornelius ,  Tony S. El-Kik ,  Stephen A. Masnica ,  Parag Parikh ,  Anthony W. Seaman

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  G11C7/222

摘要： A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

摘要翻译： 一种用于多个存储器件的信号缓冲和重定时（SBR）电路。 基于PLL的时钟发生器从接收到的主机时钟信号产生一组相移时钟信号。 多个相位选择器中的每一个独立地从该组相移时钟信号中选择连续时钟信号的子集。 连续时钟信号的每个子集被施加到一个或多个游标的不同集合，每个游标器独立地选择连续时钟信号之一作为其重新定时时钟信号，用于产生（1）输出时钟信号或重新定时位 一个或多个存储器件的地址或控制数据或（2）用于基于PLL的时钟发生器的反馈时钟信号。 SBR电路可以设计成满足与偏斜和延迟相关的相对严格的信号定时要求。

公开(公告)号：US06873650B1

公开(公告)日：2005-03-29

申请号：US09607619

申请日：2000-06-30

申请人： Raja Banerjea ,  Bahman Barazesh ,  Tony S. El-Kik ,  Kannan Rajamani

发明人： Raja Banerjea ,  Bahman Barazesh ,  Tony S. El-Kik ,  Kannan Rajamani

IPC分类号： H04B1/38 ,  H04J3/16 ,  H04L27/26

CPC分类号： H04L27/2608

摘要： A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

摘要翻译： 补偿在用户与频域中的收发器处理（例如数字多音调（DMT）收发器）之间的发送和接收路径中产生的数字样本的传输速率差异的电路。 根据本发明的示例性实施例，在接收路径中的DMT传输速率的补偿在应用诸如快速傅里叶逆变换（IFFT）的逆变换之前，由DMT收发器产生的频域系数的零填充。 对频域系数进行零填充允许通过利用与发送路径中采用的频域变换和速率匹配的速率的逆变换从频域系数生成数字样本来补偿接收路径中的传输速率。

公开(公告)号：US06404780B1

公开(公告)日：2002-06-11

申请号：US09219775

申请日：1998-12-23

申请人： Donald Raymond Laturell ,  Lane A. Smith ,  Tony S. El-kik

发明人： Donald Raymond Laturell ,  Lane A. Smith ,  Tony S. El-kik

IPC分类号： H04J306

CPC分类号： H04J3/0608 ,  H04B14/04

摘要： The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream. An interrupt is sent to the slave device by withholding the data clock signal for a predetermined amount of time. Upon receipt of the interrupt, the slave device monitors the data stream for the presence of the preamble code word. Upon detection of the preamble code word, data transmitted by the codec is again enabled.

摘要翻译： 本发明提供一种同步数据协议，其包括一个或多个串行输入输出（SIO）控制字和跨越高电压接口的数据，以允许消除帧同步信号（和相应的AC耦合电容）。 本发明对于一般的时分多路复用（TDM）数据，串行数据通信设备或同步串行通信接口以及音频编解码器设备中的控制器与编解码器之间的通信具有特别的适用性， AC '97规格，即AC Link。 通过发送数据信号线实现同步数据协议，以在两个通信设备之间提供偶尔的同步（即，不是逐帧同步）。 主设备包括前导码插入模块，用于将预定的前导码字插入到发送的数据流中。 通过在数据时钟信号中保持预定的时间量将中断发送到从设备。 在接收到中断时，从设备监视数据流以存在前导码字。 在检测到前导码字时，再次启用由编解码器发送的数据。

公开(公告)号：US07755397B2

公开(公告)日：2010-07-13

申请号：US12178286

申请日：2008-07-23

申请人： Tony S. El-Kik

发明人： Tony S. El-Kik

IPC分类号： G01R25/00 ,  H03D13/00

CPC分类号： H03L7/089 ,  G01R25/005 ,  H03L7/10

摘要： Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.

摘要翻译： 为数字相位检测提供了改进频率锁定的方法和装置。 公开了一种用于评估时钟信号和参考信号之间的相位差的相位检测器。 所公开的相位检测器在时钟信号和参考信号中的一个或多个的正边缘上对时钟信号和参考信号进行采样，在时钟信号和参考信号的一个或多个的负沿上采样时钟信号和参考信号 并产生指示时钟信号和参考信号之间的相位差的一个或多个错误信号。 可以通过产生指示时钟信号和参考信号之间的相位差的误差信号并将误差信号施加到振荡器以产生时钟信号来产生与参考信号相位对准的时钟信号。

公开(公告)号：US08664984B2

公开(公告)日：2014-03-04

申请号：US13485982

申请日：2012-06-01

申请人： Tony S. El-Kik

发明人： Tony S. El-Kik

IPC分类号： H03L7/00

CPC分类号： G06F1/12

摘要： A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

摘要翻译： 脉冲同步器电路将源 - 时钟域下生成的输入数据信号转换成目的时钟域下的输出数据信号，其中目的时钟独立于源时钟。 当源时钟比目的地时钟慢，当源时钟比目的地时钟慢时，脉冲同步器电路成功地将输入数据信号中的每个数据脉冲转换成输出数据信号中的相应数据脉冲，当输入数据 脉冲具有一个源时钟周期的持续时间，并且当输入数据脉冲具有多个源时钟周期的持续时间时。 脉冲同步器电路具有源极域电路和目标域电路。 源域电路检测输入数据脉冲，并确定它们是单周期还是多周期数据脉冲。 目标域电路基于源域电路的处理产生输出数据脉冲。