公开(公告)号：US08200877B2

公开(公告)日：2012-06-12

申请号：US12310749

申请日：2007-09-04

Applicant: Thomas Brune ,  Michael Walden ,  Oliver Kamphenkel ,  Herbert Schuetze

Inventor： Thomas Brune ,  Michael Walden ,  Oliver Kamphenkel ,  Herbert Schuetze

IPC: G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4031

Abstract: State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10 G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture.

Abstract translation: 最先进的处理器系统，尤其是 在嵌入式系统中，无法在实时条件下处理数据，特别是在接近10 Gbps的吞吐率下。 因此，当使用PCI Express（PCIe）或Infiniband或10 G-Ethernet等接口进行10 Gbps数据吞吐量时，特殊数据路径必须处理高吞吐率数据。 但是，诸如连接管理或时间不关键控制消息传递的任务更好地被处理器管理。 根据本发明，提出了一种在基于PCI Express的架构的控制和数据路径访问之间分割所需的多路复用器架构。

公开(公告)号：US08037222B2

公开(公告)日：2011-10-11

申请号：US10399272

申请日：2001-10-11

Applicant: Thomas Brune ,  Ingo Hütter

Inventor： Thomas Brune ,  Ingo Hütter

IPC: G06F13/12 ,  G05B11/01

CPC classification number: H04L12/2814 ,  H04B1/202 ,  H04L12/2805 ,  H04L12/2838 ,  H04L12/40032 ,  H04L12/40084 ,  H04L12/40117 ,  H04L2012/2849 ,  H04N21/4223 ,  H04N21/43615 ,  H04N21/43622 ,  H04N21/43632 ,  H04N21/4438 ,  H04N21/47217

Abstract: Two or more electronic devices are connected via a bus system building a cluster or chain of devices. A device can be selected using a control device, wherein an user interface for the selected device is generated based on description data which are stored in the selected device and are transferred to the control device. A single user interface is shown on a display of the control device which allows to operate at least two devices simultaneously. The user interface of a first device is displayed as main user interface and the user interface of a second device is rendered within the main interface as reduced user interface which includes only operation elements necessary for operation of the second device in combination with the first device.

Abstract translation: 两个或多个电子设备通过构建集群或设备链的总线系统连接。 可以使用控制设备来选择设备，其中，基于存储在所选择的设备中并被传送到控制设备的描述数据来生成所选设备的用户接口。 在控制设备的显示器上显示单个用户界面，其允许同时操作至少两个设备。 将第一设备的用户界面显示为主用户界面，并且将第二设备的用户界面呈现在主界面内，作为减少的用户界面，其仅包括与第一设备结合操作第二设备所需的操作元素。

公开(公告)号：US20110102636A1

公开(公告)日：2011-05-05

申请号：US12924687

申请日：2010-10-02

Applicant: Oliver Kamphenkel ,  Michael Drexler ,  Thomas Brune

Inventor： Oliver Kamphenkel ,  Michael Drexler ,  Thomas Brune

IPC: G11C16/04 ,  H04N5/76

CPC classification number: G06F12/0246 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/7203

Abstract: The invention concerns a solid state memory, comprising multiple logical units. The solid state memory contains an internal buffer for temporarily storing the incoming data steam before the incoming data are programmed to at least one page. The internal buffer keeps data that are not yet programmed in case a switch from one logical unit to another is performed. A method for operating such a device is presented.

Abstract translation: 本发明涉及一种包括多个逻辑单元的固态存储器。 固态存储器包含用于在输入数据被编程到至少一页之前临时存储输入数据蒸汽的内部缓冲器。 内部缓冲器保持尚未编程的数据，以防执行从一个逻辑单元切换到另一个逻辑单元。 介绍了一种操作这种设备的方法。

公开(公告)号：US07873797B2

公开(公告)日：2011-01-18

申请号：US10581873

申请日：2004-11-15

Applicant: Tim Niggemeier ,  Thomas Brune ,  Lothar Freissmann

Inventor： Tim Niggemeier ,  Thomas Brune ,  Lothar Freissmann

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/18

Abstract: The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.

Abstract translation: 本发明涉及一种具有外部DRAM的IC的存储器控​​制器，其中外部DRAM具有至少一个存储体并且经由至少一个通道与IC通信。 根据本发明，存储器控制器具有命令调度器，其基于用于命令的静态优先级分配和用于信道的动态优先级分配来优先考虑存储体命令的传输。

公开(公告)号：US20100332891A1

公开(公告)日：2010-12-30

申请号：US12819432

申请日：2010-06-21

Applicant: Thomas Brune ,  Michael Drexler ,  Dieter Haupt

Inventor： Thomas Brune ,  Michael Drexler ,  Dieter Haupt

IPC: G06F11/20

CPC classification number: G06F11/141 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C29/70

Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

Abstract translation: 对于写入，闪存设备以面向页面的模式进行物理访问，但是这样的设备在操作中不会出错。 根据本发明，当将总线写入周期中的信息数据以顺序的方式写入分配给公共数据总线的闪存器件中时，所述闪存器件中的至少一个不被馈送用于与所述信息数据的当前部分一起存储 。 在将当前信息数据部分写入当前所述闪速存储器件的页面的情况下发生错误的情况下，将所述当前信息数据部分写入非闪存存储器。 在下一个总线写周期期间，当包含该故障页的闪存设备通常是空闲时，该空闲时间段用于将所述信息数据的相应存储部分从所述非闪存存储器复制到该非闪存存储器的非缺陷页 闪存设备。

公开(公告)号：US07802152B2

公开(公告)日：2010-09-21

申请号：US12087708

申请日：2006-12-04

Applicant: Thomas Brune ,  Jens Peter Wittenburg

Inventor： Thomas Brune ,  Jens Peter Wittenburg

IPC: G11C29/00

CPC classification number: G11C16/10 ,  G11C29/76

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data. In case an error occurred in the current page in one or more flash devices, the content of these current pages is kept in the additional memory buffer.

Abstract translation: 用于在实时数字高带宽视频信号中进行记录或重放。 HDTV，HD渐进式或高清胶片拍摄信号，需要非常快的记忆。 用于存储流式高清视频数据可以使用基于NAND FLASH存储器的系统。 闪存设备以页面定向模式进行物理访问。 根据本发明，将输入数据以多路复用方式写入多个闪存器件的矩阵中。 执行尽可能简单和快速的列表处理，并且在矩阵架构内寻址单个闪存设备的闪存块的缺陷页面。 当以顺序方式写入时，矩阵的所有闪存设备的当前闪存设备页面的数据内容被复制到附加存储器缓冲器中的相应存储区域。 在当前系列页面已经无错误地写入闪存设备之后，附加存储器缓冲器中的相应存储区域被使能以覆盖后续页面数据。 如果一个或多个闪存设备中的当前页面发生错误，则这些当前页面的内容将保留在附加存储器缓冲区中。

公开(公告)号：US07469005B2

公开(公告)日：2008-12-23

申请号：US11086591

申请日：2005-03-22

Applicant: Thomas Brune

Inventor： Thomas Brune

IPC: H04B1/38

CPC classification number: H04L47/26 ,  H04L1/1614 ,  H04L1/1642 ,  H04L1/1809 ,  H04L1/1829 ,  H04L1/1874 ,  H04L47/10

Abstract: The invention relates to a method for synchronizing a transmitter memory area in a transmitter memory in a transmitter apparatus with a receiver memory area in a receiver memory in a receiver apparatus, and to a receiver apparatus. The transmitter memory area stores transmission data as transmission-data packets and the receiver memory area stores received data as received-data packets with associated error status data which respectively indicate an error status for the received-data packets. Before a reference identification is generated in the receiver apparatus, which, following transmission using a feedback message in the transmitter apparatus, is used for memory area synchronization, the error status data for a plurality of the received-data packets are checked in the receiver apparatus until a first received-data packet is ascertained for which the error status data indicate no error status. An identification which identifies the first received-data packet is used to ascertain an identification for the current reference received-data packet taking into account a predetermined formation rule for forming the identifications for the received-data packets, from which identification the reference identification for the current reference received-data packet is derived.

Abstract translation: 本发明涉及一种用于使发射机设备中的发射机存储器中的发射机存储器区域与接收机设备中的接收机存储器中的接收机存储区域同步的方法，以及接收机设备。 发送器存储区域将发送数据存储为发送数据分组，并且接收机存储区域将接收到的数据作为接收数据分组存储，其中相关联的错误状态数据分别指示接收数据分组的错误状态。 在接收机设备中产生参考标识之前，在接收机设备中使用发射机设备中的反馈消息进行传输之后，将其用于存储器区域同步，在接收机设备中检查多个接收数据分组的错误状态数据 直到确定错误状态数据指示没有错误状态的第一接收数据分组为止。 用于识别第一接收数据分组的标识用于确定当前参考接收数据分组的标识，考虑到用于形成接收数据分组的标识的预定形成规则，从其识别用于 导出当前参考的接收数据包。

公开(公告)号：US20050027924A1

公开(公告)日：2005-02-03

申请号：US10857255

申请日：2004-05-28

Applicant: Thomas Brune

Inventor： Thomas Brune

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/18 ,  G11B27/30 ,  G11B27/36 ,  G06F12/00

CPC classification number: G06F3/061 ,  G06F3/0638 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0677 ,  G11B27/3027 ,  G11B27/36

Abstract: Method for fast verification of sector addresses The present invention relates to a method and a device for the fast verification of sector addresses (9) in a data stream (2) obtained from a recording medium (1) upon a request from a microcontroller (13). According to the invention, the method comprises the steps of: reading the data stream (2) from the recording medium (1); decoding the data stream (2) to obtain a decoded data stream comprising user data (6) and sector addresses (9); comparing the sector addresses (9) with a range (12) of valid sector addresses; and transmitting only user data (8) having sector addresses (9) within the range (12) of valid sector addresses; whereby dedicated comparing means (10) are provided for performing the comparing step independently of the microcontroller (13).

Abstract translation: 用于快速验证扇区地址的方法本发明涉及一种用于在根据来自微控制器（13）的请求时从记录介质（1）获得的数据流（2）中快速验证扇区地址（9）的方法和装置 ）。 根据本发明，该方法包括以下步骤：从记录介质（1）读取数据流（2）; 解码数据流（2）以获得包括用户数据（6）和扇区地址（9）的解码数据流; 将扇区地址（9）与有效扇区地址的范围（12）进行比较; 以及仅传送在有效扇区地址的范围（12）内具有扇区地址（9）的用户数据（8）; 由此提供专用比较装置（10），用于独立于微控制器（13）执行比较步骤。

公开(公告)号：US20050010689A1

公开(公告)日：2005-01-13

申请号：US10487469

申请日：2002-08-22

Applicant: Jean-Baptiste Henry ,  Thomas Brune

Inventor： Jean-Baptiste Henry ,  Thomas Brune

IPC: G06F13/00 ,  G06F9/44 ,  H04L12/28 ,  H04L12/46 ,  H04L12/66 ,  H04L29/06 ,  G06F15/16

CPC classification number: H04L12/2832 ,  G06F9/451 ,  H04L12/2805 ,  H04L12/2814

Abstract: The invention concerns a 1. Method for interfacing communication between a first device on a first network and a second device on a second network, the networks being connected by an interface device, the method being carried out by the interface device and being characterized by the steps of: detecting a first message on the first network, said first message being generated by the first device, said first message being relevant for the second device; translating the first message into a format compatible with the second device; sending a second message to the second device on the second network, the second message informing the second device that the first message has been detected; upon reception of a request from the second device, transmitting the translated first message. The invention also concerns a device for implementing the method.

Abstract translation: 本发明涉及1.一种用于在第一网络上的第一设备与第二网络上的第二设备之间进行通信的接口的方法，所述网络由接口设备连接，所述方法由接口设备执行，并且其特征在于： 步骤：检测第一网络上的第一消息，所述第一消息由第一设备生成，所述第一消息与第二设备相关; 将所述第一消息转换成与所述第二设备兼容的格式; 向所述第二网络上的所述第二设备发送第二消息，所述第二消息通知所述第二设备已经检测到所述第一消息; 在接收到来自第二设备的请求时，发送所翻译的第一消息。 本发明还涉及一种用于实现该方法的装置。

公开(公告)号：US08352780B2

公开(公告)日：2013-01-08

申请号：US12819432

申请日：2010-06-21

Applicant: Thomas Brune ,  Michael Drexler ,  Dieter Haupt

Inventor： Thomas Brune ,  Michael Drexler ,  Dieter Haupt

IPC: G06F11/00

CPC classification number: G06F11/141 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C29/70

Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

Abstract translation: 对于写入，闪存设备以面向页面的模式进行物理访问，但是这样的设备在操作中不会出错。 根据本发明，当将总线写入周期中的信息数据以顺序的方式写入分配给公共数据总线的闪存器件中时，所述闪存器件中的至少一个不被馈送用于与所述信息数据的当前部分一起存储 。 如果在将当前信息数据部分写入当前所述闪速存储器件的页面中发生错误的情况下，将所述当前信息数据部分写入非闪存存储器。 在下一个总线写周期期间，当包含该故障页的闪存设备通常是空闲时，该空闲时间段用于将所述信息数据的相应存储部分从所述非闪存存储器复制到该非闪存存储器的非缺陷页 闪存设备。