公开(公告)号：US08208307B2

公开(公告)日：2012-06-26

申请号：US12772111

申请日：2010-04-30

申请人： Ting-Chang Chang ,  Fu-Yen Jian ,  Shih-Ching Chen ,  Te-Chih Chen

发明人： Ting-Chang Chang ,  Fu-Yen Jian ,  Shih-Ching Chen ,  Te-Chih Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C11/5628 ,  H01L29/792

摘要： A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.

摘要翻译： 提供了一种用于操作存储器件的方法。 根据该方法，将电荷存储在电荷存储层的源极存储区域，漏极存储区域以及与SONOS晶体管的源极，漏极和沟道对应的电荷存储层的沟道存储区域中，从而 在一个单元中实现3位信息存储。 信道存储区域通过FN隧道编程和擦除。 源极存储区域和漏极存储区域都被通道热电子编程，并通过源极侧或漏极侧FN隧道擦除。 本发明可以存储每个小区的三比特数据，从而可以显着增加存储装置的存储密度。

公开(公告)号：US20110103155A1

公开(公告)日：2011-05-05

申请号：US12841739

申请日：2010-07-22

申请人： Ting-Chang Chang ,  Te-Chih Chen ,  Fu-Yen Jian ,  Chia-Sheng Lin

发明人： Ting-Chang Chang ,  Te-Chih Chen ,  Fu-Yen Jian ,  Chia-Sheng Lin

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.

摘要翻译： 本发明的一个实施例提供一种存储装置的操作方法。 存储器件包括源极和漏极之间的源极，漏极和沟道区域，在沟道区域上具有电荷存储层的栅极电介质和栅极电介质上的栅极，其中源极，漏极和漏极 沟道区域位于衬底中。 操作方法包括以下步骤：在存储器件的栅极和漏极之间施加反向偏置，以在漏极附近的衬底中产生带对带热孔; 将带 - 带热孔注入到电荷存储层的漏极侧; 以及对存储器件执行编程/擦除操作。 通过编程/擦除操作，电荷存储层的漏极侧的带对带热孔并不完全消失。

公开(公告)号：US07983092B2

公开(公告)日：2011-07-19

申请号：US12465153

申请日：2009-05-13

申请人： Ting-Chang Chang ,  Fu-Yen Jian ,  Te-Chih Chen

发明人： Ting-Chang Chang ,  Fu-Yen Jian ,  Te-Chih Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/04

摘要： The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.

摘要翻译： 本发明涉及一种非易失性存储装置和一种使用薄膜晶体管（TFT）作为非易失性存储器的方法，该载体通过将载体存储在TFT的主体中，其通过操作将通用TFT作为非易失性存储器的存储单元来操作 TFT的电气特性，以便在LCD面板上与诸如逻辑电路或TFT-LCD像素晶体管之类的TFT形成的其它电气部件集成，而无需额外的半导体制造工艺。

公开(公告)号：US20130169351A1

公开(公告)日：2013-07-04

申请号：US13416594

申请日：2012-03-09

申请人： Ting-Chang CHANG ,  Te-Chih Chen ,  Fu-Yen Jian ,  Tien-Yu Hsieh

发明人： Ting-Chang CHANG ,  Te-Chih Chen ,  Fu-Yen Jian ,  Tien-Yu Hsieh

IPC分类号： G11C5/14

CPC分类号： G02F1/1368 ,  G02F1/13338 ,  G02F2001/13312 ,  G02F2001/13685 ,  G06F3/0412 ,  G06F3/042 ,  G09G3/36 ,  G09G2300/0465 ,  G09G2360/144 ,  H01L27/14681

摘要： A transistor operating method is applicable to a transistor including a first gate, a first gate insulating layer, a semiconductor layer, a source, a drain, a second gate insulating layer and a second gate. The transistor operating method includes: grounding the first gate and the source, applying a negative bias to the second gate and applying a positive bias to the drain, so that the transistor acts as an optical detector; alternatively, grounding the source, grounding or floating the second gate, applying a bias to the first gate and applying a positive bias to the drain, so that the transistor acts as a pixel switch.

摘要翻译： 晶体管工作方法适用于包括第一栅极，第一栅极绝缘层，半导体层，源极，漏极，第二栅极绝缘层和第二栅极的晶体管。 晶体管工作方式包括：使第一栅极和源极接地，向第二栅极施加负偏压并向漏极施加正偏置，使得晶体管用作光检测器; 源极接地，接地或浮置第二栅极，向第一栅极施加偏压并向漏极施加正偏置，使得晶体管用作像素开关。

公开(公告)号：US08339863B2

公开(公告)日：2012-12-25

申请号：US12841739

申请日：2010-07-22

申请人： Ting-Chang Chang ,  Te-Chih Chen ,  Fu-Yen Jian ,  Chia-Sheng Lin

发明人： Ting-Chang Chang ,  Te-Chih Chen ,  Fu-Yen Jian ,  Chia-Sheng Lin

IPC分类号： G11C11/34

CPC分类号： G11C16/0408 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.

摘要翻译： 本发明的一个实施例提供一种存储装置的操作方法。 存储器件包括源极和漏极之间的源极，漏极和沟道区域，在沟道区域上具有电荷存储层的栅极电介质和栅极电介质上的栅极，其中源极，漏极和漏极 沟道区域位于衬底中。 操作方法包括以下步骤：在存储器件的栅极和漏极之间施加反向偏置，以在漏极附近的衬底中产生带对带热孔; 将带 - 带热孔注入到电荷存储层的漏极侧; 以及对存储器件执行编程/擦除操作。 通过编程/擦除操作，电荷存储层的漏极侧的带对带热孔并不完全消失。

公开(公告)号：US20110096610A1

公开(公告)日：2011-04-28

申请号：US12644575

申请日：2009-12-22

申请人： Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

发明人： Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/10 ,  H01L29/792

摘要： There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.

摘要翻译： 存在使SONOS晶体管能够用作开关和存储器的方法。 通过晶体管的源极或漏极进行FN隧穿，从而进一步改变存储在与漏极或源极相邻的上部电荷存储层中的电子的状态，并且使用栅极引起的漏极泄漏的变化来识别 漏极和源的存储状态。 在此操作期间，始终保持晶体管的稳定阈值电压。 本发明使得具有开关和存储器的双重特征的单个晶体管同时具有两比特存储器效应，从而与通用晶体管相比提供了更高的存储器密度。

公开(公告)号：US20100254185A1

公开(公告)日：2010-10-07

申请号：US12465153

申请日：2009-05-13

申请人： Ting-Chang Chang ,  Fu-Yen Jian ,  Te-Chih Chen

发明人： Ting-Chang Chang ,  Fu-Yen Jian ,  Te-Chih Chen

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C16/04

摘要： The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.

摘要翻译： 本发明涉及一种非易失性存储装置和一种使用薄膜晶体管（TFT）作为非易失性存储器的方法，该载体通过将载体存储在TFT的主体中，其通过操作将通用TFT作为非易失性存储器的存储单元来操作 TFT的电气特性，以便在LCD面板上与诸如逻辑电路或TFT-LCD像素晶体管之类的TFT形成的其它电气部件集成，而无需额外的半导体制造工艺。

公开(公告)号：US08427879B2

公开(公告)日：2013-04-23

申请号：US12644575

申请日：2009-12-22

申请人： Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

发明人： Ting-Chang Chang ,  Shih-Ching Chen ,  Te-Chih Chen ,  Fu-Yen Jian ,  Yong-En Syu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/10 ,  H01L29/792

摘要： There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.

摘要翻译： 存在使SONOS晶体管能够用作开关和存储器的方法。 通过晶体管的源极或漏极进行FN隧穿，从而进一步改变存储在与漏极或源极相邻的上部电荷存储层中的电子的状态，并且使用栅极引起的漏极泄漏的变化来识别 漏极和源的存储状态。 在此操作期间，始终保持晶体管的稳定阈值电压。 本发明使得具有开关和存储器的双重特征的单个晶体管同时具有两比特存储器效应，从而与通用晶体管相比提供了更高的存储器密度。

公开(公告)号：US20110205799A1

公开(公告)日：2011-08-25

申请号：US12772111

申请日：2010-04-30

申请人： Ting-Chang CHANG ,  Fu-Yen JIAN ,  Shih-Ching CHEN ,  Te-Chih CHEN

发明人： Ting-Chang CHANG ,  Fu-Yen JIAN ,  Shih-Ching CHEN ,  Te-Chih CHEN

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C11/5628 ,  H01L29/792

摘要： A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.

摘要翻译： 提供了一种用于操作存储器件的方法。 根据该方法，将电荷存储在电荷存储层的源极存储区域，漏极存储区域以及与SONOS晶体管的源极，漏极和沟道对应的电荷存储层的沟道存储区域中，从而 在一个单元中实现3位信息存储。 信道存储区域通过FN隧道编程和擦除。 源极存储区域和漏极存储区域都被通道热电子编程，并通过源极侧或漏极侧FN隧道擦除。 本发明可以存储每个小区的三比特数据，从而可以显着增加存储装置的存储密度。