公开(公告)号：US20130170669A1

公开(公告)日：2013-07-04

申请号：US13536002

申请日：2012-06-28

Applicant: Hideaki FUKUZAWA ,  Tatsuya Ohguro ,  Akihiro Kojima ,  Yoshiaki Sugizaki ,  Mariko Takayanagi ,  Yoshihiko Fuji ,  Akio Hori ,  Michiko Hara

Inventor： Hideaki FUKUZAWA ,  Tatsuya Ohguro ,  Akihiro Kojima ,  Yoshiaki Sugizaki ,  Mariko Takayanagi ,  Yoshihiko Fuji ,  Akio Hori ,  Michiko Hara

IPC: G01L9/00 ,  B81C1/00 ,  H04R1/08

CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81C1/00246 ,  B81C2203/0771 ,  G01L9/0042 ,  H04R1/08 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00

Abstract: According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor. The transistor is provided on a semiconductor substrate. The sensing unit is provided on the semiconductor circuit unit, and has space and non-space portions. The non-space portion is juxtaposed with the space portion. The sensing unit further includes a movable beam, a strain sensing element unit, and first and second buried interconnects. The movable beam has fixed and movable portions, and includes first and second interconnect layers. The fixed portion is fixed to the non-space portion. The movable portion is separated from the transistor and extends from the fixed portion into the space portion. The strain sensing element unit is fixed to the movable portion. The first and second buried interconnects are provided in the non-space portion.

公开(公告)号：US07582940B2

公开(公告)日：2009-09-01

申请号：US11341910

申请日：2006-01-30

Applicant: Tatsuya Ohguro

Inventor： Tatsuya Ohguro

IPC: H01L27/20 ,  H01L41/08

CPC classification number: B81C1/00333 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A semiconductor device using a MEMS technology according to an example of the present invention comprises a cavity, a lower electrode positioned below the cavity, a moving part positioned in the cavity, an upper electrode coupled with the moving part, a film which covers an upper part of the cavity and has an opening, and a material which closes the opening and seals the cavity.

Abstract translation: 使用根据本发明的示例的MEMS技术的半导体器件包括腔，位于腔下方的下电极，位于空腔中的移动部分，与移动部件耦合的上电极，覆盖上部 空腔的一部分并具有开口，以及封闭开口并密封空腔的材料。

公开(公告)号：US20090127625A1

公开(公告)日：2009-05-21

申请号：US12274725

申请日：2008-11-20

Applicant: Tatsuya OHGURO

Inventor： Tatsuya OHGURO

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A semiconductor device according to one embodiment includes: a substrate; a plurality of fins made of a semiconductor and formed on the substrate; a plurality of via contact regions formed between the fins, the plurality of via contact regions and the plurality of the fins constituting a closed loop structure; a gate contact region on the substrate arranged at a position surrounded by the closed loop structure; a plurality of gate electrodes connected to the gate contact region respectively, each of the plurality of gate electrodes sandwiching both side faces of each of the plurality of fins between its opposite regions via gate insulating film; and source/drain regions formed in regions in the plurality of fins and in the contact region, the regions being formed on both sides of a region sandwiched by the gate electrodes along longitudinal direction of the fin.

Abstract translation: 根据一个实施例的半导体器件包括：衬底; 由半导体构成的多个翅片，形成在所述基板上; 形成在所述翅片之间的多个通路接触区域，所述多个通孔接触区域和所述多个翅片构成闭环结构; 所述基板上的栅极接触区域布置在由所述闭环结构包围的位置处; 多个栅极分别与栅极接触区域连接，多个栅极电极中的每一个通过栅极绝缘膜将多个翅片中的每一个的两个侧面夹在其相对区域之间; 以及源极/漏极区域，形成在多个散热片和接触区域中的区域中，所述区域形成在沿翅片的纵向方向被栅电极夹持的区域的两侧。

公开(公告)号：US07176529B2

公开(公告)日：2007-02-13

申请号：US10847314

申请日：2004-05-18

Applicant: Tatsuya Ohguro

Inventor： Tatsuya Ohguro

IPC: H01L23/62

CPC classification number: H01L27/0274

Abstract: A semiconductor device includes a semiconductor substrate having a resistivity of at least 30 Ω·cm, a first MISFET formed on the semiconductor substrate to function as a protective element, and a second MISFET protected by the first MISFET.

Abstract translation: 半导体器件包括具有至少30Ω·cm的电阻率的半导体衬底，形成在半导体衬底上用作保护元件的第一MISFET以及由第一MISFET保护的第二MISFET。

公开(公告)号：US20060261410A1

公开(公告)日：2006-11-23

申请号：US11399603

申请日：2006-04-07

Applicant: Tatsuya Ohguro

Inventor： Tatsuya Ohguro

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes a semiconductor bulk; a first insulating layer formed on the semiconductor bulk; a first semiconductor layer formed on the first insulating layer; a second insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the second insulating layer.

Abstract translation: 半导体晶片包括半导体本体; 形成在半导体本体上的第一绝缘层; 形成在所述第一绝缘层上的第一半导体层; 形成在所述第一半导体层上的第二绝缘层; 以及形成在所述第二绝缘层上的第二半导体层。

公开(公告)号：US20060209491A1

公开(公告)日：2006-09-21

申请号：US11137794

申请日：2005-05-26

Applicant: Tamio Ikehashi ,  Tatsuya Ohguro ,  Mie Matsuo

Inventor： Tamio Ikehashi ,  Tatsuya Ohguro ,  Mie Matsuo

IPC: H01G5/00

CPC classification number: H01G5/16 ,  H01G5/18

Abstract: A variable-capacitance element includes: a first electrode and a second electrode which are fixed on a substrate with a spacing; a movable electrode; an actuator which is supported on a supporting portion provided on the substrate to drive the movable electrode. The movable electrode is put in an electrically connecting state with the second electrode, when the movable electrode is driven to a first position by the actuator, and the movable electrode is put in an electrically non-connected state with the second electrode, when the movable electrode is driven to a second position by the actuator. The movable electrode is constituted to be always put in an electrically non-connected state with the first electrode.

Abstract translation: 可变电容元件包括：以间隔固定在基板上的第一电极和第二电极; 可动电极; 支撑在设置在基板上的支撑部上以驱动可动电极的致动器。 当可动电极通过致动器驱动到第一位置时，可动电极与第二电极处于电连接状态，并且可移动电极与第二电极处于与电不连接的状态，当可移动电极 电极被致动器驱动到第二位置。 可动电极构成为与第一电极总是处于非连接状态。

公开(公告)号：US20060163694A1

公开(公告)日：2006-07-27

申请号：US11315598

申请日：2005-12-23

Applicant: Tatsuya Ohguro

Inventor： Tatsuya Ohguro

IPC: H01L29/00

CPC classification number: H01L27/08 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An element isolation region is formed in a surface region of a semiconductor substrate. A spiral-shaped inductor is formed above the element isolation region. A conductive region to which a constant potential is applied is formed inside the inner circumference of the inductor.

Abstract translation: 元件隔离区域形成在半导体衬底的表面区域中。 螺旋形电感器形成在元件隔离区域上方。 在电感器的内周形成有施加恒定电位的导电区域。

公开(公告)号：US20060098059A1

公开(公告)日：2006-05-11

申请号：US11094320

申请日：2005-03-31

Applicant: Tatsuya Ohguro ,  Tamio Ikehashi ,  Mie Matsuo ,  Shuichi Sekine

Inventor： Tatsuya Ohguro ,  Tamio Ikehashi ,  Mie Matsuo ,  Shuichi Sekine

IPC: B41J2/045

CPC classification number: H03H9/173 ,  B81B3/0018 ,  G02B26/0858 ,  H01G5/18 ,  H01H2057/006 ,  H01L27/20 ,  H01L41/094 ,  H01L41/0946 ,  H01L41/0973 ,  H03H9/0542 ,  H03H9/587 ,  H03H2003/027 ,  H03H2009/241

Abstract: A semiconductor device having a surface MEMS element, includes a semiconductor substrate, and an actuator which is arranged above the semiconductor substrate via a space and has a lower electrode, an upper electrode, and a piezoelectric layer sandwiched between the lower electrode and the upper electrode, at least an entire surface of the piezoelectric layer being substantially flat.

Abstract translation: 具有表面MEMS元件的半导体器件包括半导体衬底和致动器，其经由空间设置在半导体衬底的上方，并且具有夹在下电极和上电极之间的下电极，上电极和压电层 至少压电层的整个表面基本上是平的。

公开(公告)号：US06894331B2

公开(公告)日：2005-05-17

申请号：US09734658

申请日：2000-12-13

Applicant: Takashi Yoshitomi ,  Tatsuya Ohguro ,  Ryoji Hasumi ,  Hideki Kimijima ,  Takashi Yamaguchi ,  Masahiro Inohara

Inventor： Takashi Yoshitomi ,  Tatsuya Ohguro ,  Ryoji Hasumi ,  Hideki Kimijima ,  Takashi Yamaguchi ,  Masahiro Inohara

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805

Abstract: At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.

Abstract translation: 目前，Cu（铜）被用作布线材料。 在作为RF模拟装置和CMOS逻辑装置的组合的RF-CMOS装置中，MIM电容器的两个电极由具有大扩散系数的Cu形成。 为了防止Cu向MIM电容器的电容器绝缘膜扩散，具有防止扩散的功能的扩散防止膜插入电容器绝缘膜和两个电极之间。 结果，形成电极的Cu不扩散到电容器绝缘膜。

公开(公告)号：US5736767A

公开(公告)日：1998-04-07

申请号：US675720

申请日：1996-07-02

Applicant: Takashi Yoshitomi ,  Tatsuya Ohguro

Inventor： Takashi Yoshitomi ,  Tatsuya Ohguro

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0928 ,  H01L29/7833 ,  H01L29/7838

Abstract: A semiconductor device including a CMOSFET having first and second channel type MOSFETs, respectively formed in a first semiconductor region of a first conductivity type and in a second semiconductor region of a second conductivity type. The first channel type MOSFET has a first gate electrode insulatively formed on the first region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, first source/drain regions of the second conductivity type respectively formed in the first region and having a LDD structure, and a buried channel region of the second conductivity type formed just below the first gate electrode. The second channel type MOSFET has a second gate electrode insulatively formed on the second region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, second source/drain regions of the first conductivity type respectively formed in the second region and having a LDD structure.

Abstract translation: 一种半导体器件，包括具有第一和第二沟道型MOSFET的CMOSFET，分别形成在第一导电类型的第一半导体区域和第二导电类型的第二半导体区域中。 第一沟道型MOSFET具有第一栅极电极，绝缘地形成在第一区域上，由第一导电型半导体制成，栅极长度为0.2μm以下，第二导电类型的第一源极/漏极区分别形成在 所述第一区域具有LDD结构，以及形成在所述第一栅电极正下方的所述第二导电类型的掩埋沟道区。 第二沟道型MOSFET具有在第二区域上隔绝地形成的第二栅电极，由第一导电型半导体制成，栅极长度为0.2μm以下，第一导电类型的第二源/漏区分别形成在 第二区域并具有LDD结构。