公开(公告)号：US07679539B2

公开(公告)日：2010-03-16

申请号：US12076876

申请日：2008-03-25

Applicant: Da-Huei Lee ,  Tai-Haur Kuo

Inventor： Da-Huei Lee ,  Tai-Haur Kuo

IPC: H03M1/66

CPC classification number: H03M1/0673 ,  H03M1/74 ,  H03M3/502

Abstract: A randomized thermometer-coding digital-to-analog converter (DAC) for the reduction of harmonic distortion due to non-ideal circuit mismatch is presented. The present invention introduces a new dynamic element matching technique that contains three properties of randomization, consecutive selection and less element switching activity to achieve good spurious-free dynamic range and small maximum output error. The topology uses a bank of 1-bit DAC elements, whose outputs are summed to produce a multi-level analog output. The binary digital input is encoded to be thermometer code. During a randomization period, the thermometer code is barrel-shifted to a specific starting position where the position is generated randomly. Thus, the DAC noise is randomized with less element switching activity and consecutive selection.

Abstract translation: 提出了一种用于减少由于非理想电路失配引起的谐波失真的随机温度计编码数模转换器（DAC）。 本发明引入了一种新的动态元素匹配技术，其包含随机化，连续选择和较少元件切换活动的三个特性，以实现良好的无杂散动态范围和小的最大输出误差。 该拓扑结构使用一组1位DAC元件，其输出相加以产生多电平模拟输出。 二进制数字输入被编码为温度计代码。 在随机化期间，温度计代码被桶形移位到随机生成位置的特定起始位置。 因此，DAC噪声随机化，具有更少的元件切换活动和连续选择。

公开(公告)号：US07576675B1

公开(公告)日：2009-08-18

申请号：US12076882

申请日：2008-03-25

Applicant: Da-Huei Lee ,  Tai-Haur Kuo

Inventor： Da-Huei Lee ,  Tai-Haur Kuo

IPC: H03M1/66

CPC classification number: H03M1/0818 ,  H03M1/742

Abstract: A return-to-zero current-steering DAC is presented. The presented return-to-zero technique can isolate the analog output nodes of the DAC from the coupling of the control signals of the DAC without sacrificing speed. The topology uses a bank of return-to-zero circuits, which employs return-to-zero and isolation transistors to implement the presented return-to-zero technique.

Abstract translation: 提出了一种归零电流导向DAC。 所提出的归零技术可以将DAC的模拟输出节点与DAC的控制信号的耦合隔离，而不会牺牲速度。 该拓扑结构使用一组归零电路，其采用归零和隔离晶体管来实现所提出的归零技术。

公开(公告)号：US20060251270A1

公开(公告)日：2006-11-09

申请号：US11308770

申请日：2006-05-02

Applicant: Cheng-Chung Yang ,  Li-Ping Chu ,  Tai-Haur Kuo

Inventor： Cheng-Chung Yang ,  Li-Ping Chu ,  Tai-Haur Kuo

IPC: H04B15/00

CPC classification number: H03F1/305

Abstract: An anti-pop device for audio amplifier is suitable for outputting signals to a speaker to produce sound waves. The audio amplifier comprises a pre-processing unit, a filter and a voltage level detection unit electrically connected to the pre-processing unit. The voltage level detection unit detects the supply voltage. As the supply voltage is lower than a predetermined value, the voltage level detection unit outputs a signal to the pre-processing unit for lowering the audio volume so that a pop noise caused by circuit malfunction resulted from excessively-low supply voltage can be prevented.

Abstract translation: 用于音频放大器的反弹性装置适用于向扬声器输出信号以产生声波。 音频放大器包括预处理单元，滤波器和电连接到预处理单元的电压电平检测单元。 电压电平检测单元检测电源电压。 当电源电压低于预定值时，电压电平检测单元向预处理单元输出用于降低音频音量的信号，从而可以防止由电源电压过低导致的电路故障引起的弹出噪声。

公开(公告)号：US06304608B1

公开(公告)日：2001-10-16

申请号：US09186316

申请日：1998-11-04

Applicant: Kuan-Dar Chen ,  Tai-Haur Kuo

Inventor： Kuan-Dar Chen ,  Tai-Haur Kuo

IPC: H03M300

CPC classification number: H03M3/35 ,  H03M1/0665 ,  H03M3/424 ,  H03M3/452 ,  H03M3/464

Abstract: A method for reducing baseband tones and intermodulation distortions in a multibit sigma-delta converter employing dynamic element matching is disclosed. An N-level sigma-delta analog-to-digital converter includes an analog loop filter, an N-level quantizer, an element selection logic, an internal N-level digital-to-analog converter (DAC), and a decimation filter, where N is an integer greater than two. Adding k extra unit elements to the internal N-level DAC, which totally comprises (N−1+k) unit elements, can shift the sigma-delta modulator tones and intermodulation distortions outside the baseband with no change to the quantization levels of the internal N-level DAC, where k is a positive integer. A cyclical selection of (N−1+k) unit elements in the internal N-level DAC is in accordance with an element selection logic which receives an output of the N-level quantizer and produces a set of control signals for the element selection of the internal N-level DAC. The present invention can also be applied to a multibit sigma-delta digital-to-analog converter.

Abstract translation: 公开了一种用于减少采用动态元件匹配的多位Σ-Δ转换器中的基带频调和互调失真的方法。 N电平Σ-Δ模数转换器包括模拟环路滤波器，N电平量化器，元件选择逻辑，内部N电平数模转换器（DAC）和抽取滤波器， 其中N是大于2的整数。 将全部包含（N-1 + k）个单元的内部N级DAC添加k个额外的单位元件可以在基带外部移位Σ-Δ调制器调制和互调失真，而不改变内部的量化电平 N级DAC，其中k是正整数。 内部N电平DAC中的（N-1 + k）个单元元件的周期性选择符合接收N电平量化器的输出并产生用于元件选择的一组控制信号的元件选择逻辑 内部N级DAC。 本发明还可以应用于多位Σ-Δ数模转换器。

公开(公告)号：US5623263A

公开(公告)日：1997-04-22

申请号：US546494

申请日：1995-10-20

Applicant: Tai-Haur Kuo ,  Wen-Bin Lin ,  Chun-Hsien Su ,  Jhy-Rong Chen ,  Wen-Chyi Wang

Inventor： Tai-Haur Kuo ,  Wen-Bin Lin ,  Chun-Hsien Su ,  Jhy-Rong Chen ,  Wen-Chyi Wang

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/448 ,  H03M3/43

Abstract: The invention relates to a high performance and absolute stable 4th-order sigma-delta modulator with leapfrog topology which contains the following key components: (a) four integrators for integrating the difference signal between the input and reconstruct signal; (b) three add/subtract adders for adding or subtracting analog signal; (c) three loop coefficient control members for controlling the performance and stability of the modulator, (d) an analog-to-digital converter (A/D converter) for quantizing the output signals of the fourth integrator to digital codes, and (e) a digital-to-analog converter (D/A converter) for converting the digital codes to analog signals.

Abstract translation: 本发明涉及具有跨越拓扑结构的高性能和绝对稳定的四阶Σ-Δ调制器，其包含以下关键部件：（a）用于对输入和重建信号之间的差分信号进行积分的四个积分器; （b）三个加减法模拟信号的加法器; （c）用于控制调制器的性能和稳定性的三个环路系数控制部件，（d）用于将第四积分器的输出信号量化为数字代码的模数转换器（A / D转换器），（e ）用于将数字代码转换为模拟信号的数模转换器（D / A转换器）。

公开(公告)号：US5033069A

公开(公告)日：1991-07-16

申请号：US390792

申请日：1989-08-08

Applicant: Hung C. Lin ,  Tai-Haur Kuo

Inventor： Hung C. Lin ,  Tai-Haur Kuo

IPC: H03K25/04 ,  H03K29/00

CPC classification number: B82Y10/00 ,  H03K25/04 ,  H03K29/00

Abstract: The disclosure is directed to an electronic circuit and method for counting input electrical signals. An embodiment of the method of the invention includes the following steps: providing a device having a current versus voltage characteristic with a plurality of peaks, and negative resistance regions between the peaks; generating a triggering pulse in response to each input signal to be counted, and applying said triggering pulse to the device to change the voltage across the device; and outputting the voltage across the device as an indication of the number of received input signals. The device may be a resonant tunneling diode with multiple peaks in its current versus voltage characteristic. The preferred embodiment of the method of the invention includes the step of providing a load resistance means across the device. In this embodiment, the triggering pulse is operative to change the voltage across the device to a stable operating point of the device in conjunction with the load resistance means. Also in this embodiment, the step of providing a triggering pulse comprises providing a current pulse whose magnitude depends on the present stable operating point of the device in conjunction with the load resistance means. The counting technique and apparatus of the present invention operates at high speed and without undue complexity.

Abstract translation: 本公开涉及用于对输入电信号进行计数的电子电路和方法。 本发明方法的一个实施例包括以下步骤：提供具有多个峰值的电流对电压特性的装置和峰值之间的负电阻区域; 响应于要被计数的每个输入信号产生触发脉冲，以及将所述触发脉冲施加到所述装置以改变所述装置两端的电压; 并且输出跨设备的电压作为接收到的输入信号的数量的指示。 该器件可以是在其电流对电压特性中具有多个峰值的谐振隧道二极管。 本发明方法的优选实施例包括在整个装置上提供负载电阻装置的步骤。 在该实施例中，触发脉冲可操作以结合负载电阻装置将装置两端的电压改变到装置的稳定工作点。 同样在该实施例中，提供触发脉冲的步骤包括提供电流脉冲，其大小取决于装置的当前稳定工作点以及负载电阻装置。 本发明的计数技术和装置高速运转，没有过多的复杂性。

公开(公告)号：US20090243904A1

公开(公告)日：2009-10-01

申请号：US12076876

申请日：2008-03-25

Applicant: DA-HUEI LEE ,  TAI-HAUR KUO

Inventor： DA-HUEI LEE ,  TAI-HAUR KUO

IPC: H03M1/12

CPC classification number: H03M1/0673 ,  H03M1/74 ,  H03M3/502

Abstract: A randomized thermometer-coding digital-to-analog converter (DAC) for the reduction of harmonic distortion due to non-ideal circuit mismatch is presented. The present invention introduces a new dynamic element matching technique that contains three properties of randomization, consecutive selection and less element switching activity to achieve good spurious-free dynamic range and small maximum output error. The topology uses a bank of 1-bit DAC elements, whose outputs are summed to produce a multi-level analog output. The binary digital input is encoded to be thermometer code. During a randomization period, the thermometer code is barrel-shifted to a specific starting position where the position is generated randomly. Thus, the DAC noise is randomized with less element switching activity and consecutive selection.

Abstract translation: 提出了一种用于减少由于非理想电路失配引起的谐波失真的随机温度计编码数模转换器（DAC）。 本发明引入了一种新的动态元素匹配技术，其包含随机化，连续选择和较少元件切换活动的三个特性，以实现良好的无杂散动态范围和小的最大输出误差。 该拓扑结构使用一组1位DAC元件，其输出相加以产生多电平模拟输出。 二进制数字输入被编码为温度计代码。 在随机化期间，温度计代码被桶形移位到随机生成位置的特定起始位置。 因此，DAC噪声随机化，具有更少的元件切换活动和连续选择。

公开(公告)号：US20070007912A1

公开(公告)日：2007-01-11

申请号：US11456093

申请日：2006-07-07

Applicant: Cheng-Chung Yang ,  Da-Huei Lee ,  Tai-Haur Kuo

Inventor： Cheng-Chung Yang ,  Da-Huei Lee ,  Tai-Haur Kuo

IPC: H05B41/36

CPC classification number: H02M1/32 ,  H03K17/0822 ,  H03K17/6872

Abstract: A power output device includes a bridged output stage, a reference voltage generator and a detecting unit to compare the output voltages from the aforementioned two units. The bridged output stage may be implemented by a full-bridge or a half-bridge configuration. The reference voltage generator is symmetric to the bridged output stage to generate a reference voltage, which is served as a reference voltage range for the voltage difference of the two terminals of the turned-on transistors in the bridged output stage during operation. When the detecting unit detects the voltages across the two terminals of the turned-on transistors in the bridged output stage exceed the reference voltage range, all the transistors are turned off and no power is outputted to the load. Therefore, the circuit is capable of preventing damages caused by a large current due to overload or short circuit.

Abstract translation: 功率输出装置包括桥接输出级，参考电压发生器和用于比较来自前述两个单元的输出电压的检测单元。 桥接输出级可以通过全桥或半桥配置来实现。 参考电压发生器对称于桥接输出级，以产生参考电压，其作为运行期间桥接输出级中的导通晶体管的两个端子的电压差的参考电压范围。 当检测单元检测到桥接输出级中的导通晶体管的两端的电压超过参考电压范围时，所有晶体管都截止，而不向负载输出功率。 因此，该电路能够防止由于过载或短路引起的大电流造成的损坏。

公开(公告)号：US5113188A

公开(公告)日：1992-05-12

申请号：US391221

申请日：1989-08-08

Applicant: Tai-Haur Kuo ,  Hung C. Lin

Inventor： Tai-Haur Kuo ,  Hung C. Lin

IPC: H03M1/36

CPC classification number: B82Y10/00 ,  H03M1/368

Abstract: An analog-to-digital converter circuit is disclosed for receiving an analog input signal and producing a digital output having a plurality of binary bits representative of the input signal. A number of devices are utilized, each of which has a voltage versus current characteristic with a plurality of peaks, and negative resistance regions between said peaks. In the illustrated embodiments, these devices are resonant tunneling diodes. For each bit to be produced, a pair of said devices are provided, each being coupled in series arrangement with a resistor. Predetermined portions of the input signal are applied to both of the series arrangements for each respective bit to be produced. Signals from both of the series arrangements are combined for each respective bit to be produced. The combined outputs respectively represent the produced binary bits. In the preferred embodiment, the means for applying predetermined portions of the input signal comprises means for applying different fractional portions of the input signal to respective pairs of series arrangements. In this embodiment, the input signal comprises an input voltage, and a voltage offset is applied to the input signal. The transition between states ("0" to "1", or vice versa) is very fast due to the high switching speed of the narrow negative resistance region of the RTD's I-V characteristic. Also, because of the judicious use of offsets, the quantization uncertainty is one-half the last significant bit size.

Abstract translation: 公开了一种用于接收模拟输入信号并产生具有表示输入信号的多个二进制位的数字输出的模拟 - 数字转换器电路。 利用多个器件，每个器件具有多个峰值的电压 - 电流特性，以及所述峰值之间的负电阻区域。 在所示的实施例中，这些器件是谐振隧穿二极管。 对于要产生的每个位，提供一对所述器件，每个器件与电阻器串联布置。 将输入信号的预定部分应用于要产生的每个相应位的串联装置。 对于要生产的每个相应的位组合来自两个串联装置的信号。 组合输出分别表示产生的二进制位。 在优选实施例中，用于施加输入信号的预定部分的装置包括用于将输入信号的不同分数部分应用于各对串联装置的装置。 在本实施例中，输入信号包括输入电压，并且电压偏移被施加到输入信号。 由于RTD的I-V特性的窄负电阻区域的高开关速度，状态之间的转变（“0”至“1”，反之亦然）非常快。 此外，由于明智地使用偏移量，量化不确定度是最后一个有效位大小的一半。

公开(公告)号：US20100134079A1

公开(公告)日：2010-06-03

申请号：US12553383

申请日：2009-09-03

Applicant: Jia-Ming LIU ,  Yeong-Chau Kuo ,  Tai-Haur Kuo

Inventor： Jia-Ming LIU ,  Yeong-Chau Kuo ,  Tai-Haur Kuo

IPC: G05F1/10

CPC classification number: H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

Abstract: An analog variable-frequency controller includes a first current generator, a second current generator, a clock generator and a light/heavy load selector. The first and second current generator receive a load current signal and then output a first voltage signal and a second voltage signal, respectively. The clock generator generates a corresponding switching frequency according to the first voltage signal or the second voltage signal. The light/heavy load selector, connected with the first current generator, the second current generator and the clock generator, receives a control signal for controlling the clock generator to receive the first voltage signal or the second voltage signal. The abovementioned controller is implemented by an analog circuit, which has a lower circuit complexity, lower cost and is easy to be integrated into a switching converter.

Abstract translation: 模拟可变频率控制器包括第一电流发生器，第二电流发生器，时钟发生器和轻/重负载选择器。 第一和第二电流发生器接收负载电流信号，然后分别输出第一电压信号和第二电压信号。 时钟发生器根据第一电压信号或第二电压信号产生相应的开关频率。 与第一电流发生器，第二电流发生器和时钟发生器连接的轻/重负载选择器接收用于控制时钟发生器的控制信号以接收第一电压信号或第二电压信号。 上述控制器由模拟电路实现，模拟电路具有较低的电路复杂度，较低的成本，易于集成到开关转换器中。