公开(公告)号：US07709330B2

公开(公告)日：2010-05-04

申请号：US11745574

申请日：2007-05-08

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US07601614B2

公开(公告)日：2009-10-13

申请号：US11213056

申请日：2005-08-26

申请人： Sung Ku Kwon ,  Young Kyun Cho ,  Jong Dae Kim

发明人： Sung Ku Kwon ,  Young Kyun Cho ,  Jong Dae Kim

IPC分类号： H01L21/30

CPC分类号： H01L21/76243 ,  H01L21/76254

摘要： A process for manufacturing a silicon on insulator (SOI) substrate is described. The process includes forming a buried oxidation layer in a first wafer and forming an oxidation layer on the first wafer. A buried hydrogen layer is formed in the first wafer deeper than the buried oxidation layer. A second wafer is bonded onto the first oxidation layer. The first wafer is removed below the buried hydrogen layer to expose the first wafer between the buried oxidation layer and the buried hydrogen layer. The exposed first wafer and the buried oxidation layer are sequentially removed to expose the first wafer between the buried oxidation layer and the first oxidation layer. Finally, a predetermined thickness of the first wafer exposed in the previous step is removed. Accordingly, a highly uniform and ultra thin SOI substrate is formed without employing a CMP process.

摘要翻译： 描述了一种用于制造绝缘体上硅（SOI）衬底的工艺。 该方法包括在第一晶片中形成掩埋氧化层，并在第一晶片上形成氧化层。 在第一晶片中形成比埋入氧化层更深的埋置氢层。 第二晶片结合到第一氧化层上。 在掩埋氢层下方移除第一晶片，以暴露掩埋氧化层和掩埋氢层之间的第一晶片。 依次去除暴露的第一晶片和掩埋氧化层，以在掩埋氧化层和第一氧化层之间露出第一晶片。 最后，去除在前一步骤中暴露的第一晶片的预定厚度。 因此，在不使用CMP工艺的情况下形成高度均匀且超薄的SOI衬底。

公开(公告)号：US07335945B2

公开(公告)日：2008-02-26

申请号：US11012695

申请日：2004-12-16

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

IPC分类号： H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78645

摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.

摘要翻译： 提供一种多栅极MOS晶体管及其制造方法。 垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。 因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

公开(公告)号：US07332774B2

公开(公告)日：2008-02-19

申请号：US11727268

申请日：2007-03-26

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

公开(公告)号：US07276430B2

公开(公告)日：2007-10-02

申请号：US11232722

申请日：2005-09-21

申请人： Sung Ku Kwon

发明人： Sung Ku Kwon

IPC分类号： H01L21/30

CPC分类号： H01L21/76243 ,  H01L21/76256

摘要： Provided is a method of manufacturing a silicon on insulator (SOI) substrate, which includes the steps of (a) forming a buried oxidation layer to a predetermined depth of a first wafer and forming an oxidation layer on a surface of the first wafer; (b) bonding a second wafer onto the first wafer; (c) selectively removing the oxidation layer so as to expose a bottom surface of the first wafer; (d) selectively removing the exposed bottom silicon layer of the first wafer using the buried oxidation layer as an etch stop layer; and (e) removing the buried oxidation layer to expose a top surface of the first wafer, and thinning the exposed top surface of the first wafer to a predetermined thickness, so that a process can be relatively simple and can be readily carried out, thereby manufacturing an SOI substrate having a uniform silicon thickness of high quality and an ultra thin characteristic.

摘要翻译： 提供了一种制造绝缘体上硅（SOI）衬底的方法，其包括以下步骤：（a）将掩埋氧化层形成到第一晶片的预定深度并在第一晶片的表面上形成氧化层; （b）将第二晶片接合到所述第一晶片上; （c）选择性地除去氧化层以暴露第一晶片的底表面; （d）使用掩埋氧化层作为蚀刻停止层选择性地去除第一晶片的暴露的底部硅层; 和（e）去除掩埋氧化层以暴露第一晶片的顶表面，并将暴露的第一晶片的顶表面变薄到预定厚度，使得工艺可以相对简单并且可以容易地进行，从而 制造具有高质量和超薄特性的均匀硅厚度的SOI衬底。

公开(公告)号：US07208356B2

公开(公告)日：2007-04-24

申请号：US10989006

申请日：2004-11-16

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

公开(公告)号：US07403178B2

公开(公告)日：2008-07-22

申请号：US10817838

申请日：2004-04-06

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Sung Ku Kwon ,  Byoung Gon Yu

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Sung Ku Kwon ,  Byoung Gon Yu

IPC分类号： G09G3/30 ,  G09G3/20 ,  G09G3/22

CPC分类号： G09G3/30 ,  G09G2310/027 ,  G09G2320/0276

摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.

摘要翻译： 提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度 的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

公开(公告)号：US07233018B2

公开(公告)日：2007-06-19

申请号：US11182671

申请日：2005-07-15

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L29/06 ,  H01L31/00

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减小导致跨导（Gm）的增益，结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US20060128116A1

公开(公告)日：2006-06-15

申请号：US11213056

申请日：2005-08-26

申请人： Sung Ku Kwon ,  Young Kyun Cho ,  Jong Dae Kim

发明人： Sung Ku Kwon ,  Young Kyun Cho ,  Jong Dae Kim

IPC分类号： H01L21/46

CPC分类号： H01L21/76243 ,  H01L21/76254

摘要： Provided is a method of manufacturing a silicon on insulator (SOI) substrate. The method includes the steps of: (a) forming a buried oxidation layer to a predetermined depth of a first wafer and forming an oxidation layer on the first wafer; (b) forming a buried hydrogen layer in the first wafer to a depth larger than the buried oxidation layer; (c) bonding a second wafer onto the first oxidation layer; (d) removing the first wafer below the buried hydrogen layer so as to expose the first wafer between the buried oxidation layer and the buried hydrogen layer; (e) sequentially removing the exposed first wafer and the buried oxidation layer so as to expose the first wafer between the buried oxidation layer and the first oxidation layer; and (f) removing a predetermined thickness of the first wafer exposed in the step of sequentially removing the exposed first wafer. As a result, a CMP process accompanying a high cost which has been applied in the related art is not employed, so that a process can be relatively simple and readily carried out, thereby manufacturing an SOI substrate having a uniform characteristic of high quality and an ultra thin characteristic.

摘要翻译： 提供一种制造绝缘体上硅（SOI）衬底的方法。 该方法包括以下步骤：（a）将掩埋氧化层形成到第一晶片的预定深度并在第一晶片上形成氧化层; （b）在所述第一晶片中形成深度大于所述掩埋氧化层的深度的掩埋氢层; （c）将第二晶片接合到所述第一氧化层上; （d）移除掩埋氢层下方的第一晶片，以便在掩埋氧化层和掩埋氢层之间露出第一晶片; （e）依次去除所述暴露的第一晶片和所述掩埋氧化层，以使所述第一晶片暴露于所述掩埋氧化层和所述第一氧化层之间; 和（f）去除在顺序地除去暴露的第一晶片的步骤中暴露的第一晶片的预定厚度。 结果，不采用伴随现有技术中应用的高成本的CMP工艺，从而可以相对简单且容易地进行处理，从而制造具有均匀的高品质特性的SOI衬底和 超薄特性。

公开(公告)号：US20050007315A1

公开(公告)日：2005-01-13

申请号：US10739735

申请日：2003-12-17

申请人： Yil-Suk Yang ,  Byung-Doo Kim ,  Jong-Dae Kim ,  Tae-Moon Roh ,  Dae-Woo Lee ,  Byoung-Gon Yu ,  Il-Yong Park ,  Sung-Ku Kwon

发明人： Yil-Suk Yang ,  Byung-Doo Kim ,  Jong-Dae Kim ,  Tae-Moon Roh ,  Dae-Woo Lee ,  Byoung-Gon Yu ,  Il-Yong Park ,  Sung-Ku Kwon

IPC分类号： G09G3/30 ,  G09G3/32

CPC分类号： G09G3/3283 ,  G09G3/3241 ,  G09G2310/027 ,  G09G2330/021

摘要： Disclosed is a low power and high density source driver and a current driven active matrix organic electroluminescent device having the same, in which all elements operate at a normal voltage and all circuits of the source driver are shielded from a high voltage of a panel. The source driver includes: a shift register for generating an enable signal for storing data; a data latch circuit for storing digital data inputted from an exterior; a line latch circuit for sequentially storing the data in response to the enable signal and outputting the stored data in parallel at one time in response to a load signal; a current type digital-to-analog converter for converting the digital data outputted from the line latch circuit into an analog signal, the analog signal being outputted in a form of a current signal; and a high voltage shield circuit for transferring the output of the current digital-to-analog converter to source lines of an external panel and for shielding internal circuits from a high voltage of the panel. The shift register, the data latch circuit, the line latch circuit, the current type digital-to-analog converter and the high voltage shield circuit are driven at a normal voltage.

摘要翻译： 公开了一种低功率和高密度源极驱动器以及具有这种驱动器的电流驱动有源矩阵有机电致发光器件，其中所有元件都工作在正常电压，并且源极驱动器的所有电路都屏蔽了面板的高电压。 源极驱动器包括：移位寄存器，用于产生用于存储数据的使能信号; 数据锁存电路，用于存储从外部输入的数字数据; 行锁存电路，用于响应于使能信号顺序地存储数据并响应于负载信号一次并行地输出存储的数据; 用于将从线路锁存电路输出的数字数据转换为模拟信号的电流型数模转换器，模拟信号以电流信号的形式输出; 以及用于将当前数模转换器的输出传送到外部面板的源极线并用于屏蔽内部电路与面板的高电压的高压屏蔽电路。 移位寄存器，数据锁存电路，线路锁存电路，电流型数模转换器和高压屏蔽电路以正常电压驱动。