公开(公告)号：US4757504A

公开(公告)日：1988-07-12

申请号：US854449

申请日：1986-04-21

申请人： Mark A. Stambaugh ,  Stephen P. Sacarisen

发明人： Mark A. Stambaugh ,  Stephen P. Sacarisen

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.

摘要翻译： 一种用于在总线周期的一个或多个阶段期间在数据总线上产生多位数据值的奇偶校验的多相奇偶校验发生器电路。 该电路包括具有可耦合到相应输入数据线对的多个并行解码电路的预置电路。 每个解码电路具有奇数和偶数输出线，用于分别响应于相关联的行线对上的奇数或偶数1（或0）来提供输出信号。 电路包括预充电放电电路，其耦合到预置电路，用于响应于输入数据线上的奇数1产生第一奇偶校验信号，响应于输入数据上的偶数1，产生第二奇偶校验信号 线条。

公开(公告)号：US4827242A

公开(公告)日：1989-05-02

申请号：US939663

申请日：1986-12-09

申请人： Gene E. Blankenship ,  Edward M. Gonsalves ,  Keith W. Kawate ,  Stephen P. Sacarisen ,  William H. Giolma ,  Damir A. Spanjol

发明人： Gene E. Blankenship ,  Edward M. Gonsalves ,  Keith W. Kawate ,  Stephen P. Sacarisen ,  William H. Giolma ,  Damir A. Spanjol

IPC分类号： G01N17/02 ,  B60Q1/00

CPC分类号： G01N17/02 ,  F01P2025/70 ,  F01P2025/80

摘要： A dual function sensor particularly useful with vehicular coolant systems indicates when a coolant liquid becomes corrosive to such cooling system materials as well as when the liquid falls to a low level condition. A reference and a sense electrode are used to probe the condition of the coolant liquid. Integral electronics provide signal conditioning and transmitting to indicate both corrosive and low level coolant conditions. The sensor assembly mounted directly onto a tubular coupling on the vehicle radiator by pushing the assembly onto the coupling until a spring wire element snaps past a lip formed on the free distal end of the coupling. An electrical connector shroud extends from the assembly and accommodates a mating male connector which is pushed onto the shroud until a clip mounted on the male connector snaps over a locking tab located on the shroud. The male connector typically is connected to an engine control module (ECM).

摘要翻译： 特别适用于车辆冷却剂系统的双重功能传感器指示冷却剂液体何时腐蚀这种冷却系统材料以及当液体降至低水平状态时。 使用参考电极和感测电极来探测冷却剂液体的状态。 集成电子设备提供信号调理和传输，以指示腐蚀性和低水平冷却剂条件。 传感器组件通过将组件推到联接器上直接安装在车辆辐射器上的管状联接器上，直到弹簧丝元件穿过形成在联接器的自由远端上的唇缘。 电连接器护罩从组件延伸并且容纳配合的阳连接器，该连接器被推到护罩上，直到安装在阳连接器上的夹子卡在位于护罩上的锁定舌片上。 公连接器通常连接到发动机控制模块（ECM）。

公开(公告)号：US4646232A

公开(公告)日：1987-02-24

申请号：US567596

申请日：1984-01-03

申请人： Ki S. Chang ,  Michael W. Patrick ,  Stephen P. Sacarisen ,  Mark A. Stambaugh

发明人： Ki S. Chang ,  Michael W. Patrick ,  Stephen P. Sacarisen ,  Mark A. Stambaugh

IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F13/38 ,  H04L12/433 ,  G06F13/00

CPC分类号： H04L12/433 ,  G06F13/128 ,  G06F13/362 ,  G06F13/385

摘要： A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

摘要翻译： 用作闭环，令牌传递，局域网类型的通信环路的适配器的微处理器设备。 环上的每个站具有主机处理器，主机CPU，主存储器和系统总线。 微处理器设备相对独立于主机CPU，通过系统总线耦合到主存储器，并且包括本地CPU，本地读/写存储器，片上定时器，本地总线和总线仲裁器。 发射/接收控制器连接在环和微处理器设备之间。 该控制器耦合到本地总线，以便直接访问本地读/写存储器，也在总线仲裁器的控制下。 本地CPU执行从由本地总线访问的ROM获取的指令，因此本地CPU指令获取，用于发送或接收数据帧的发送/接收控制器的直接存储器访问以及来自主机CPU的复制传输或 接收到的消息帧，全部争夺当地的总线。 使用适当优先级的总线仲裁来控制对本地总线的访问。 由本地总线访问的片上定时器提供用于监视和控制通信协议的时间段。

公开(公告)号：US4792835A

公开(公告)日：1988-12-20

申请号：US938226

申请日：1986-12-05

申请人： Stephen P. Sacarisen ,  Gene E. Blankenship ,  Rajiv R. Shah ,  Toan Tran ,  David J. Myers ,  Johnson J. Lin ,  Steve Thompson

发明人： Stephen P. Sacarisen ,  Gene E. Blankenship ,  Rajiv R. Shah ,  Toan Tran ,  David J. Myers ,  Johnson J. Lin ,  Steve Thompson

IPC分类号： H01L21/82 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  H01L27/112 ,  H01L29/78 ,  B44C1/22 ,  C23F1/02 ,  H01L21/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A process for making a metal fuse link in a MOS or CMOS process which includes depositing a refractory metal or metal alloy over an already deposited multi-level oxide and patterning the deposited metal or metal alloy so that it has a fusing segment between and integral with expanded segments such that the length and cross sectional area of the fusing segment is sufficiently small so that the fusing current therethrough is less than 20 milliamperes. The fuse and surrounding circuitry is covered with a passivation layer and contacts formed in the passivation layer to the expanded segments.

摘要翻译： 一种用于在MOS或CMOS工艺中制造金属熔断体的工艺，其包括在已沉积的多层氧化物上沉积难熔金属或金属合金，并对沉积的金属或金属合金进行图案化，使得其具有与 扩展段使得熔断段的长度和横截面面积足够小，使得其中的熔化电流小于20毫安。 保险丝和周围电路覆盖有钝化层和形成在钝化层中的扩展段的触点。

公开(公告)号：US4777591A

公开(公告)日：1988-10-11

申请号：US922362

申请日：1986-10-23

申请人： Ki S. Chang ,  Michael W. Patrick ,  Stephen P. Sacarisen ,  Mark A. Stambaugh

发明人： Ki S. Chang ,  Michael W. Patrick ,  Stephen P. Sacarisen ,  Mark A. Stambaugh

IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F13/38 ,  H04L12/433 ,  G06F13/18

CPC分类号： G06F13/128 ,  G06F13/362 ,  G06F13/385 ,  H04L12/433

摘要： A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

摘要翻译： 公开了一种用作闭环，令牌传递，局域网类型的通信环路的适配器的微处理器设备。 环上的每个站具有主机处理器，主机CPU，主存储器和系统总线。 其中相对独立于主机CPU操作并且通过系统总线耦合到主存储器的微处理器设备包括本地CPU，本地读/写存储器，片上定时器，本地总线和总线 仲裁者。 发射/接收控制器连接在环和微处理器设备之间。 该控制器耦合到本地总线，以便直接访问本地读/写存储器，也在总线仲裁器的控制下。 本地CPU执行从由本地总线访问的ROM获取的指令，因此本地CPU指令获取，用于发送或接收数据帧的发送/接收控制器的直接存储器访问以及来自主机CPU的复制传输或 接收到的消息帧，全部争夺当地的总线。 使用适当优先级的总线仲裁来控制对本地总线的访问。 由本地总线访问的片上定时器提供用于监视和控制通信协议的时间段。

公开(公告)号：US4666582A

公开(公告)日：1987-05-19

申请号：US780467

申请日：1985-09-26

申请人： Gene E. Blankenship ,  Edward M. Gonsalves ,  Keith W. Kawate ,  Stephen P. Sacarisen ,  William H. Giolma ,  Damir A. Spanjol

发明人： Gene E. Blankenship ,  Edward M. Gonsalves ,  Keith W. Kawate ,  Stephen P. Sacarisen ,  William H. Giolma ,  Damir A. Spanjol

IPC分类号： G01N17/02 ,  G01N27/26

CPC分类号： G01N17/02 ,  F01P2025/70 ,  F01P2025/80

摘要： A dual function sensor particularly useful with vehicular coolant systems indicates when a coolant liquid becomes corrosive to such cooling system materials as well as when the liquid falls to a low level condition. A reference and a sense electrode are used to probe the condition of the coolant liquid. Integral electronics provide signal conditioning and transmitting to indicate both corrosive and low level coolant conditions. The sensor assembly mounts directly onto a tubular coupling on the vehicle radiator by pushing the assembly onto the coupling until a spring wire element snaps past a lip formed on the free distal end of the coupling. An electrical connector shroud extends from the assembly and accommodates a mating male connector which is pushed onto the shroud until a clip mounted on the male connector snaps over a locking tab located on the shroud. The male connector typically is connected to an engine control module (ECM).

公开(公告)号：US4641308A

公开(公告)日：1987-02-03

申请号：US567598

申请日：1984-01-03

申请人： Stephen P. Sacarisen ,  Otto N. Fanini

发明人： Stephen P. Sacarisen ,  Otto N. Fanini

IPC分类号： G06F11/267 ,  G06F13/12 ,  G06F13/362 ,  G06F13/38 ,  H04L12/433 ,  G06F11/00

CPC分类号： G06F11/2236 ,  G06F13/128 ,  G06F13/362 ,  G06F13/385 ,  H04L12/433

摘要： A microprocessor device is used in an adapter for a communications loop of the closed ring, one-way, token-passing local area network type. Each station has a host processor with a host CPU, a main memory, and a system bus, and has an adapter including the microprocessor tested according to the invention. The adapter coupled to the main memory by the system bus and includes a local CPU (the microprocessor), a local read/write memory, and a local bus. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station receives a free token, the transmit-and-receive controller copies the message frame to be transmitted from the local read/write memory to the outgoing signal path, converting from parallel to serial. When a message addressed to this station is received, the controller converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus. Testing of the microprocessor is accomplished by internal self-test of the registers of the device, using the microcode of the control ROM initiated by a test control input.

摘要翻译： 在适配器中使用微处理器设备，用于闭环，单向，令牌传递的局域网类型的通信环路。 每个站具有主机处理器，其具有主机CPU，主存储器和系统总线，并且具有包括根据本发明测试的微处理器的适配器。 适配器通过系统总线耦合到主存储器，并且包括本地CPU（微处理器），本地读/写存储器和本地总线。 发送和接收控制器耦合到本地总线，以直接访问本地读/写存储器; 当本台接收到免费令牌时，发送和接收控制器将要从本地读/写存储器发送的消息帧复制到输出信号路径，从并行转换为串行。 当收到寻址到本站的消息时，控制器将其从串行转换为并行，并通过本地总线将消息帧复制到本地读/写存储器中。 微处理器的测试是通过使用由测试控制输入启动的控制ROM的微码来对器件的寄存器进行内部自检来实现的。

公开(公告)号：US4571675A

公开(公告)日：1986-02-18

申请号：US567599

申请日：1984-01-03

申请人： Mark A. Stambaugh ,  Stephen P. Sacarisen ,  Michael W. Patrick

发明人： Mark A. Stambaugh ,  Stephen P. Sacarisen ,  Michael W. Patrick

IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F13/38 ,  H04L12/433 ,  G06F1/00

CPC分类号： H04L12/433 ,  G06F13/128 ,  G06F13/362 ,  G06F13/385

摘要： A microprocessor device with an on-chip integrated auto-loaded timer is used in an adapter for a communications loop of the token-passing local area network type. The network has a number of stations coupled to a closed one-way signal path, and each station has a host processor with a host CPU and memory. The microprocessor device with integrated auto-loaded timer is part of an adapter coupled to the host processor. A message frame to be transmitted is copied into a local read/write memory in the adapter by way of the host system bus and a local bus, under initiation by the host CPU. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station has access to the loop (i.e., receives a free token) the transmit-and-receive controller copies the message frame from the local read/write memory to the outgoing signal path, converting from parallel to serial. When the transmit-and-receive controller receives a message addressed to this station, it converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus, interrupting the local CPU. The message frame is then copied from the local read/write memory to the main memory.

摘要翻译： 具有片上集成自动加载定时器的微处理器设备用于令牌传递局域网类型的通信环路的适配器中。 网络具有耦合到闭合单向信号路径的多个站，并且每个站具有主机处理器，其具有主机CPU和存储器。 具有集成自动加载定时器的微处理器设备是耦合到主处理器的适配器的一部分。 要发送的消息帧通过主机系统总线和本地总线在主机CPU启动时被复制到适配器中的本地读/写存储器中。 发送和接收控制器耦合到本地总线，以直接访问本地读/写存储器; 当该站具有访问环路（即，接收空闲令牌）时，发送和接收控制器将消息帧从本地读/写存储器复制到输出信号路径，从并行转换为串行。 当发送和接收控制器收到寻址到该站的消息时，将其从串行转换为并行，并通过本地总线将消息帧复制到本地读/写存储器中，从而中断本地CPU。 然后将消息帧从本地读/写存储器复制到主存储器。

公开(公告)号：US5204657A

公开(公告)日：1993-04-20

申请号：US706152

申请日：1991-05-28

申请人： Robert L. Prosser ,  Stephen P. Sacarisen

发明人： Robert L. Prosser ,  Stephen P. Sacarisen

IPC分类号： G08B21/24

CPC分类号： G08B21/24

摘要： A locating device has a locating circuit having a oscillator/counter logic circuit, a reset circuit, a reset beep circuit, an enable flip-flop, a delay flip-flop, a mux (multiplexer) flip-flop a mux logic circuit and a piezo oscillator circuit. The locating device is generally designed to assist the user to locate an object of which the locating device is a part. The preferred embodiment of the device is especially useful to determine the location of a misplaced television remote control. The alternative embodiment of the device could also be used to locate an object such as a credit card, locate an animal when lost or to find person on which the device is carried as a game. The locating device may also be used to reduce the occurrences of misplacement of objects or items (credit cards, ID cards, etc.) from their proper place or to alert a person when the object or item is in an improper place. The alternative embodiment has mode switch to control the audio alarm emission cycle.

摘要翻译： 定位装置具有定位电路，其具有振荡器/计数器逻辑电路，复位电路，复位蜂鸣电路，使能触发器，延迟触发器，复用器（多路复用器）触发器复用逻辑电路和 压电振荡电路。 定位装置通常设计成帮助用户定位定位装置是其一部分的物体。 该装置的优选实施例对于确定放错放置的电视遥控器的位置特别有用。 设备的替代实施例也可以用于定位诸如信用卡的对象，丢失时定位动物或者找到设备作为游戏携带的人。 定位装置还可以用于减少物体或物品（信用卡，身份证等）从适当位置的错位发生，或者当物体或物品处于不正确的位置时提醒人。 替代实施例具有用于控制音频报警发射周期的模式切换。

公开(公告)号：US4403284A

公开(公告)日：1983-09-06

申请号：US210105

申请日：1980-11-24

申请人： Stephen P. Sacarisen ,  Karl M. Guttag

发明人： Stephen P. Sacarisen ,  Karl M. Guttag

IPC分类号： G06F9/26

CPC分类号： G06F9/268

摘要： A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction is executed in a sequence of microstates which are generated by selecting an entry point for the first address in a control ROM then continuing with a series of jumps and/or further entry points determined by the instruction and by the current state of the microprocessor. Improved circuitry is provided for selecting the entry point using a minimum of space on the chip by detecting the position of the leading 1 bit. Thus an instruction set can be used in which different groups of instructions have different numbers of leading zero bits.

摘要翻译： MOS / LSI型单片微处理器器件包含一个ALU，多个内部总线，多个地址/数据寄存器，以及一个带相关控制解码或微控制器电路的指令寄存器。 该设备通过双向复用的地址/数据总线和多个控制线与外部存储器和外设进行通信。 每个指令以微观状态的顺序执行，该微状态是通过选择控制ROM中的第一地址的入口点而产生的，然后继续进行由指令确定的一系列跳跃和/或另外的入口点以及微处理器的当前状态 。 提供了改进的电路，用于通过检测前导1位的位置，使用芯片上的最小空间来选择入口点。 因此，可以使用指令集，其中不同的指令组具有不同数量的前导零比特。