公开(公告)号：US06458648B1

公开(公告)日：2002-10-01

申请号：US09466715

申请日：1999-12-17

Applicant: Simon J. Molloy ,  Nace Layadi ,  Edward Belden Harris ,  Sidhartha Sen

Inventor： Simon J. Molloy ,  Nace Layadi ,  Edward Belden Harris ,  Sidhartha Sen

IPC: H01L218242

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/32136

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

公开(公告)号：US20090267145A1

公开(公告)日：2009-10-29

申请号：US12108045

申请日：2008-04-23

Applicant: Charles Walter Pearce ,  Simon J. Molloy ,  Shuming Xu ,  Xiao Rui Li

Inventor： Charles Walter Pearce ,  Simon J. Molloy ,  Shuming Xu ,  Xiao Rui Li

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer.

Abstract translation: 形成金属氧化物半导体（MOS）器件的方法包括以下步骤：形成第一导电类型的半导体层，其具有第二导电类型的源极和漏极区域，沟道区域和形成的轻掺杂漏极区域 其中 在靠近半导体层的上表面的沟道区上形成栅极; 在形成步骤之后，在半导体层的上表面上沉积具有第一厚度的第一介电层; 在靠近栅极的轻掺杂漏极上的区域中蚀刻第一介电层以减小其厚度; 在所述第一介电层上沉积具有第二厚度的第二介电层，所述第二介电层包括在所述蚀刻区域中，所述第二厚度小于所述第一厚度; 以及在所述第二电介质层上形成屏蔽电极。

公开(公告)号：US06472307B1

公开(公告)日：2002-10-29

申请号：US09491644

申请日：2000-01-27

Applicant: Donald C. Dennis ,  Nace Layadi ,  Simon J. Molloy ,  Kurt G. Steiner ,  Sylvia W. Thomas

Inventor： Donald C. Dennis ,  Nace Layadi ,  Simon J. Molloy ,  Kurt G. Steiner ,  Sylvia W. Thomas

IPC: H01L21316

CPC classification number: H01L21/76837 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably involves etching with a reactive ion etch.

Abstract translation: 本发明提供一种制造在厚金属特征上具有覆盖层的集成电路的方法。 在一个实施例中，该方法包括在厚金属特征上形成第一和第二氧化物层，通过蚀刻第一和第二氧化物层形成包含氧化物间隔物的复合氧化物层，并在复合氧化物层上形成覆盖层。 更具体地，形成第一氧化物层涉及使用高密度等离子体（HDP）工艺，形成第二氧化物层涉及使用等离子体增强化学气相沉积（PECVD）工艺，并且形成复合氧化物层优选包括用反应离子 蚀刻。

公开(公告)号：US06258610B1

公开(公告)日：2001-07-10

申请号：US09347313

申请日：1999-07-02

Applicant: James W. Blatchford ,  Scott Jessen ,  Brittin C. Kane ,  Nace Layadi ,  John M. McIntosh ,  Simon J. Molloy

Inventor： James W. Blatchford ,  Scott Jessen ,  Brittin C. Kane ,  Nace Layadi ,  John M. McIntosh ,  Simon J. Molloy

IPC: G01R3126

CPC classification number: H01L22/12

Abstract: A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments are processed using an auto-correlation function to produce an auto-correlation signal for each characteristic surface portion of the patterned feature. A reference signal having signal segments corresponding to characteristic surface portions of a known patterned feature is provided and each segment of the auto-correlation signal is compared to the respective signal segments of the reference signal.

Abstract translation: 公开了一种用于分析表面上具有图案特征的半导体表面的方法。 扫描至少一个图案特征以产生具有对应于图案化特征的特征表面部分的信号段的扫描波形信号。 使用自相关函数处理信号段，以对图案化特征的每个特征表面部分产生自相关信号。 提供具有对应于已知图案特征的特征表面部分的信号段的参考信号，并将自相关信号的每个段与参考信号的相应信号段进行比较。

公开(公告)号：US06656850B2

公开(公告)日：2003-12-02

申请号：US10215170

申请日：2002-08-08

Applicant: Simon J. Molloy ,  Nace Layadi ,  Edward Belden Harris ,  Sidhartha Sen

Inventor： Simon J. Molloy ,  Nace Layadi ,  Edward Belden Harris ,  Sidhartha Sen

IPC: H01L21362

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/32136

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

公开(公告)号：US06265235B1

公开(公告)日：2001-07-24

申请号：US09383154

申请日：1999-08-25

Applicant: John M. McIntosh ,  Erik C. Houge ,  Brittin C. Kane ,  Simon J. Molloy ,  Catherine Vartuli

Inventor： John M. McIntosh ,  Erik C. Houge ,  Brittin C. Kane ,  Simon J. Molloy ,  Catherine Vartuli

IPC: H01L2166

CPC classification number: H01L22/12 ,  Y10S977/855

Abstract: A non-destructive method for evaluating a topographical feature 16 of an integrated circuit 42, such as a photoresist runner, includes core sectioning the feature to remove a small section 22, without damage to the remainder of the wafer 36 on which the integrated circuit is formed. A tool having fine adjustment, such as a micromanipulator with a rod-shaped probe 24 in the form of a glass needle, is used to remove the section for examination and metrology. The section is separated from the underlying substrate surface 14 and can be examined from all sides. Variations in a critical dimension, such as line width W, along the length L of the section, as well as average measurements of the dimension, can be obtained.

Abstract translation: 用于评估集成电路42（例如光致抗蚀剂流道）的地形特征16的非破坏性方法包括将该特征切除以去除小部分22的芯，而不损坏其上集成电路的晶片36的其余部分 形成。 使用具有精细调节的工具，例如具有玻璃针形式的棒状探针24的显微操纵器，用于去除用于检查和计量的部分。 该部分与下面的基底表面14分离，并且可以从所有侧面进行检查。 可以获得沿截面长度L的临界尺寸（例如线宽W）的变化以及尺寸的平均测量值。

公开(公告)号：US06218085B1

公开(公告)日：2001-04-17

申请号：US09400406

申请日：1999-09-21

Applicant: Simon J. Molloy ,  Nace Layadi ,  Allen Yen ,  Brian D. Crevasse ,  Steven A. Lytle

Inventor： Simon J. Molloy ,  Nace Layadi ,  Allen Yen ,  Brian D. Crevasse ,  Steven A. Lytle

IPC: G03F736

CPC classification number: G03F7/427

Abstract: A method for stripping photoresist material (26) from a semiconductor substrate (16) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (24). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.

Abstract translation: 用于从半导体衬底（16）剥离光致抗蚀剂材料（26）的方法避免了从返工溶剂中引入钠和其它污染物离子。 氧和氢等离子体混合物剥离光致抗蚀剂材料，而不会在氧化钛层（24）内显着引入氧气。 通过将衬底暴露于无氧还原等离子体（例如含氢等离子体）中，氮化钛的任何氧化反转。 因此，氮化钛层比在等离子体剥离过程中已经被广泛氧化的层更难于掺杂污染物离子以进行随后的返工溶剂清洗。