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    Methods of Forming Patterns and Methods of Manufacturing Semiconductor Devices Using the Same
    1.
    发明申请
    Methods of Forming Patterns and Methods of Manufacturing Semiconductor Devices Using the Same 有权
    形成图案的方法和使用其制造半导体器件的方法

    公开(公告)号：US20110312172A1

    公开(公告)日：2011-12-22

    申请号：US13164215

    申请日：2011-06-20

    Applicant: Min-Joon Park ,  Seok-Hyun Lim

    Inventor： Min-Joon Park ,  Seok-Hyun Lim

    IPC: H01L21/3205 ,  H01L21/311

    CPC classification number: H01L21/32139 ,  H01L21/3086 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/11541

    Abstract: In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.

    Abstract translation: 在形成图案的方法中，通过使用蚀刻掩模的第一蚀刻工艺对衬底上的层进行构图，以形成多个第一初步图案和多个第二预备图案。 第二初步图案在第二距离处彼此间隔开，第二距离大于第一预备图案间隔开的第一距离。 第一和第二涂层分别形成在第一和第二初步图案的侧壁上，并且通过使用蚀刻掩模的第二蚀刻工艺去除第一和第二涂层以及第一和第二初步图案的部分以形成多个 的第一图案和多个第二图案。 第一图案的宽度小于第一初步图案的宽度。 第一图案可以具有相对于基底的大致垂直的侧壁。

    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING CAPACITORS HAVING HIGH-ASPECT RATIO SUPPORT PATTERNS AND RELATED DEVICES
    2.
    发明申请
    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING CAPACITORS HAVING HIGH-ASPECT RATIO SUPPORT PATTERNS AND RELATED DEVICES 失效
    制造集成电路设备的方法，包括具有高比例支持模式的电容器及相关设备

    公开(公告)号：US20080186648A1

    公开(公告)日：2008-08-07

    申请号：US12021929

    申请日：2008-01-29

    Applicant: Yong-Hee Choi ,  Young-Kyu Cho ,  Sung-II Cho ,  Seok-Hyun Lim

    Inventor： Yong-Hee Choi ,  Young-Kyu Cho ,  Sung-II Cho ,  Seok-Hyun Lim

    IPC: H01G4/008 ,  H01G7/00

    CPC classification number: H01G4/005 ,  H01G4/33 ,  H01L27/0203 ,  H01L27/10852 ,  H01L28/90 ,  Y10T29/435

    Abstract: A method of fabricating an integrated circuit device includes forming a plurality of lower capacitor electrodes vertically extending from a substrate. The plurality of lower capacitor electrodes respectively include an inner sidewall and an outer sidewall. At least one support pattern is formed vertically extending between ones of the plurality of lower capacitor electrodes from top portions thereof opposite the substrate and along the outer sidewalls thereof towards the substrate to a depth that is greater than a lateral distance between adjacent ones of the plurality of lower capacitor electrodes. A dielectric layer is formed on the support pattern and on outer sidewalls of the plurality of lower capacitor electrodes, and an upper capacitor electrode is formed on the dielectric layer. Related devices are also discussed.

    Abstract translation: 一种制造集成电路器件的方法包括形成从衬底垂直延伸的多个下电容器电极。 多个下电容电极分别包括内侧壁和外侧壁。 至少一个支撑图案形成为从多个下部电容器电极中的多个下部电容器电极的顶部与衬底相对并且沿着其外侧壁朝向衬底形成垂直延伸的深度，该深度大于多个下部电容器电极中的相邻电极电极之间的横向距离 的下电容器电极。 在支撑图案和多个下电容器电极的外侧壁上形成介电层，在电介质层上形成上电容电极。 还讨论了相关设备。

    Methods of forming patterns and methods of manufacturing semiconductor devices using the same
    5.
    发明授权
    Methods of forming patterns and methods of manufacturing semiconductor devices using the same 有权
    形成图案的方法和使用其制造半导体器件的方法

    公开(公告)号：US09054054B2

    公开(公告)日：2015-06-09

    申请号：US13164215

    申请日：2011-06-20

    Applicant: Min-Joon Park ,  Seok-Hyun Lim

    Inventor： Min-Joon Park ,  Seok-Hyun Lim

    IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/308 ,  H01L27/115 ,  H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/32139 ,  H01L21/3086 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/11541

    Abstract: In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.

    Abstract translation: 在形成图案的方法中，通过使用蚀刻掩模的第一蚀刻工艺对衬底上的层进行构图，以形成多个第一初步图案和多个第二预备图案。 第二初步图案在第二距离处彼此间隔开，第二距离大于第一预备图案间隔开的第一距离。 第一和第二涂层分别形成在第一和第二初步图案的侧壁上，并且通过使用蚀刻掩模的第二蚀刻工艺去除第一和第二涂层以及第一和第二初步图案的部分以形成多个 的第一图案和多个第二图案。 第一图案的宽度小于第一初步图案的宽度。 第一图案可以具有相对于基底的大致垂直的侧壁。

    Method of forming patterns for semiconductor device
    7.
    发明授权
    Method of forming patterns for semiconductor device 有权
    形成半导体器件图案的方法

    公开(公告)号：US08551888B2

    公开(公告)日：2013-10-08

    申请号：US13238945

    申请日：2011-09-21

    Applicant: Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

    Inventor： Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11568

    Abstract: A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.

    Abstract translation: 一种形成半导体器件的图案的方法。 该方法包括：在要蚀刻的层上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层，其中所述第二硬掩模层包括形成在所述第一部分下面的第一部分和第二部分，其中所述第一部分和第二部分由相同的材料构成; 蚀刻第一部分以形成第一图案; 形成覆盖所述第一图案的侧壁的间隔物; 使用间隔物蚀刻第二部分作为蚀刻掩模以形成第二图案; 使用设置在间隔物下方的第二图案作为蚀刻掩模来蚀刻第一硬掩模层和间隔物以形成第三图案; 并使用第三图案蚀刻待蚀刻的层。

    METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
    形成半导体器件的图案的方法

    公开(公告)号：US20120129349A1

    公开(公告)日：2012-05-24

    申请号：US13238945

    申请日：2011-09-21

    Applicant: Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

    Inventor： Yun-seung Kang ,  Jong-chul Park ,  Kwang-yong Yang ,  Sang-sup Jeong ,  Seok-hyun Lim

    IPC: H01L21/308

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11568

    Abstract: A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.

    Abstract translation: 一种形成半导体器件的图案的方法。 该方法包括：在要蚀刻的层上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层，其中所述第二硬掩模层包括形成在所述第一部分下面的第一部分和第二部分，其中所述第一部分和第二部分由相同的材料构成; 蚀刻第一部分以形成第一图案; 形成覆盖所述第一图案的侧壁的间隔物; 使用间隔物蚀刻第二部分作为蚀刻掩模以形成第二图案; 使用设置在间隔物下方的第二图案作为蚀刻掩模来蚀刻第一硬掩模层和间隔物以形成第三图案; 并使用第三图案蚀刻待蚀刻的层。

    Process Control Methods and Systems
    9.
    发明申请
    Process Control Methods and Systems 审中-公开
    过程控制方法和系统

    公开(公告)号：US20100120178A1

    公开(公告)日：2010-05-13

    申请号：US12616510

    申请日：2009-11-11

    Applicant: Seok-Hyun Lim ,  Myeong-Cheol Kim ,  Yong-Jin Kim ,  Moon-Sang Lee ,  Ki-Chul Hwang

    Inventor： Seok-Hyun Lim ,  Myeong-Cheol Kim ,  Yong-Jin Kim ,  Moon-Sang Lee ,  Ki-Chul Hwang

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  H01L22/20

    Abstract: A process control method includes setting first through fourth conditions, forming a first pattern by performing a first process on a semiconductor wafer, measuring the first pattern using a first measuring equipment to obtain a first result, comparing the first result with the first condition, forming a second pattern by performing a second process on the semiconductor wafer, comparing a period of the second process with the second condition, measuring the second pattern using a second measuring equipment to obtain a second result, comparing the second result with the third condition, forming a third pattern by performing a third process on the semiconductor wafer, measuring the third pattern using the a second measuring equipment to obtain a third result, and comparing the third result with the fourth condition.

    Abstract translation: 一种处理控制方法，包括设置第一至第四条件，通过在半导体晶片上执行第一处理形成第一图案，使用第一测量设备测量第一图案以获得第一结果，将第一结果与第一条件进行比较，形成 第二模式，通过在半导体晶片上执行第二处理，将第二处理的周期与第二条件进行比较，使用第二测量设备测量第二模式以获得第二结果，将第二结果与第三条件进行比较，形成 通过在半导体晶片上进行第三处理，使用第二测量设备测量第三图案以获得第三结果，并将第三结果与第四条件进行比较，从而形成第三图案。

    Methods of fabricating integrated circuit devices including capacitors having high-aspect ratio support patterns and related devices
    10.
    发明授权
    Methods of fabricating integrated circuit devices including capacitors having high-aspect ratio support patterns and related devices 失效
    制造集成电路器件的方法，包括具有高纵横比支持图案和相关器件的电容器

    公开(公告)号：US07869189B2

    公开(公告)日：2011-01-11

    申请号：US12021929

    申请日：2008-01-29

    Applicant: Yong-Hee Choi ,  Young-Kyu Cho ,  Sung-Il Cho ,  Seok-Hyun Lim

    Inventor： Yong-Hee Choi ,  Young-Kyu Cho ,  Sung-Il Cho ,  Seok-Hyun Lim

    IPC: H01G4/228

    CPC classification number: H01G4/005 ,  H01G4/33 ,  H01L27/0203 ,  H01L27/10852 ,  H01L28/90 ,  Y10T29/435

    Abstract: A method of fabricating an integrated circuit device includes forming a plurality of lower capacitor electrodes vertically extending from a substrate. The plurality of lower capacitor electrodes respectively include an inner sidewall and an outer sidewall. At least one support pattern is formed vertically extending between ones of the plurality of lower capacitor electrodes from top portions thereof opposite the substrate and along the outer sidewalls thereof towards the substrate to a depth that is greater than a lateral distance between adjacent ones of the plurality of lower capacitor electrodes. A dielectric layer is formed on the support pattern and on outer sidewalls of the plurality of lower capacitor electrodes, and an upper capacitor electrode is formed on the dielectric layer. Related devices are also discussed.

    Abstract translation: 一种制造集成电路器件的方法包括形成从衬底垂直延伸的多个下电容器电极。 多个下电容电极分别包括内侧壁和外侧壁。 至少一个支撑图案形成为从多个下部电容器电极中的多个下部电容器电极的顶部与衬底相对并且沿着其外侧壁朝向衬底形成垂直延伸的深度，该深度大于多个下部电容器电极中的相邻电极电极之间的横向距离 的下电容器电极。 在支撑图案和多个下电容器电极的外侧壁上形成介电层，在电介质层上形成上电容电极。 还讨论了相关设备。

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