公开(公告)号：US07939855B2

公开(公告)日：2011-05-10

申请号：US12538747

申请日：2009-08-10

Applicant: Sang-Yeop Han ,  Se-Ra Won

Inventor： Sang-Yeop Han ,  Se-Ra Won

IPC: H01L27/10

CPC classification number: H01L21/823481

Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.

Abstract translation: 半导体器件包括衬底，设置在衬底上的第一，第二和第三栅极线，第一和第二栅极线限定具有第一纵横比的第一沟槽，第二栅极线和第三栅极线限定具有第二方面的第二沟槽 形成为减小第一和第二纵横比的第一绝缘层，以及设置在第一绝缘层上以填充第一和第二沟槽的第二绝缘层。

公开(公告)号：US07572720B2

公开(公告)日：2009-08-11

申请号：US11617592

申请日：2006-12-28

Applicant: Sang-Yeop Han ,  Se-Ra Won

Inventor： Sang-Yeop Han ,  Se-Ra Won

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/823481

Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.

Abstract translation: 半导体器件包括衬底，设置在衬底上的第一，第二和第三栅极线，第一和第二栅极线限定具有第一纵横比的第一沟槽，第二栅极线和第三栅极线限定具有第二方面的第二沟槽 形成为减小第一和第二纵横比的第一绝缘层，以及设置在第一绝缘层上以填充第一和第二沟槽的第二绝缘层。

公开(公告)号：US20080272431A1

公开(公告)日：2008-11-06

申请号：US12174735

申请日：2008-07-17

Applicant: Jong Man KIM ,  Chang Goo LEE ,  Jong Sik KIM ,  Se Ra WON

Inventor： Jong Man KIM ,  Chang Goo LEE ,  Jong Sik KIM ,  Se Ra WON

IPC: H01L29/78

CPC classification number: H01L21/28061 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L29/66621

Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.

Abstract translation: 具有形成在半导体器件中的可变宽度凹部的变宽的凹槽栅极结构可以充分增加形成在可变宽度凹部中的栅极的晶体管的沟道长度，从而有效地减小漏电流并提高刷新特性。 在制造凹槽栅结构的方法中，进行两次或更多次的蚀刻，以形成在衬底中具有变化的宽度的栅极凹槽，并且在栅极凹部中形成栅极。

公开(公告)号：US20090294770A1

公开(公告)日：2009-12-03

申请号：US12538747

申请日：2009-08-10

Applicant: Sang-Yeop HAN ,  Se-Ra Won

Inventor： Sang-Yeop HAN ,  Se-Ra Won

IPC: H01L29/786

CPC classification number: H01L21/823481

Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.

Abstract translation: 半导体器件包括衬底，设置在衬底上的第一，第二和第三栅极线，第一和第二栅极线限定具有第一纵横比的第一沟槽，第二栅极线和第三栅极线限定具有第二方面的第二沟槽 形成为减小第一和第二纵横比的第一绝缘层，以及设置在第一绝缘层上以填充第一和第二沟槽的第二绝缘层。

公开(公告)号：US07413969B2

公开(公告)日：2008-08-19

申请号：US11318960

申请日：2005-12-27

Applicant: Jong Man Kim ,  Chang Goo Lee ,  Jong Sik Kim ,  Se Ra Won

Inventor： Jong Man Kim ,  Chang Goo Lee ,  Jong Sik Kim ,  Se Ra Won

IPC: H01L21/3205

CPC classification number: H01L21/28061 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L29/66621

Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.

Abstract translation: 具有形成在半导体器件中的可变宽度凹部的变宽的凹槽栅极结构可以充分增加形成在可变宽度凹部中的栅极的晶体管的沟道长度，从而有效地减小漏电流并提高刷新特性。 在制造凹槽栅结构的方法中，进行两次或更多次的蚀刻，以形成在衬底中具有变化的宽度的栅极凹槽，并且在栅极凹部中形成栅极。

公开(公告)号：US20070215875A1

公开(公告)日：2007-09-20

申请号：US11617592

申请日：2006-12-28

Applicant: Sang-Yeop Han ,  Se-Ra Won

Inventor： Sang-Yeop Han ,  Se-Ra Won

IPC: H01L31/00

CPC classification number: H01L21/823481

Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.

Abstract translation: 半导体器件包括衬底，设置在衬底上的第一，第二和第三栅极线，第一和第二栅极线限定具有第一纵横比的第一沟槽，第二栅极线和第三栅极线限定具有第二方面的第二沟槽 形成为减小第一和第二纵横比的第一绝缘层，以及设置在第一绝缘层上以填充第一和第二沟槽的第二绝缘层。