公开(公告)号：US06839783B2

公开(公告)日：2005-01-04

申请号：US09732135

申请日：2000-12-07

Applicant: Roshan J. Samuel ,  Brian J. Karguth ,  Gregory L. Christison

Inventor： Roshan J. Samuel ,  Brian J. Karguth ,  Gregory L. Christison

IPC: G06F13/14 ,  G06F3/00 ,  G06F13/40 ,  H03K5/00 ,  H03K19/0175 ,  G06F13/00

CPC classification number: G06F13/4072

Abstract: A state machine interface that can be used with digital devices whose interface characteristics are not known in advance. This interface is completely programmable on a clock-by-clock basis. The interface consists of an output component, which can be either a control register or a data bus, and an input component that can be combined to provide various input/output (I/O) functions. The state machine interface of this invention makes it possible to interface with many type of application devices, whose interface characteristics and/or waveforms may not be identical or are not known at the time a particular state machine is designed.

公开(公告)号：US07159083B2

公开(公告)日：2007-01-02

申请号：US10319238

申请日：2002-12-13

Applicant: Roshan J. Samuel ,  Jason D. Kridner

Inventor： Roshan J. Samuel ,  Jason D. Kridner

IPC: G06F12/00 ,  G06F13/00 ,  G06F7/38

CPC classification number: G05B19/056 ,  G05B2219/13009 ,  G05B2219/13108

Abstract: The programmable transition state machine of this invention is designed to allow implementation of hardware capable of increasing the performance of critical encoding and decoding tasks in a microprocessor environment where a required encoding or decoding or machines is not known in advance. The state machine described may also be used in systems that need flexibility to support a wide variety of functions or machines or where a hardwired approach is not useful. This unique state machine processes the state information and the transition from a present state to a next state in CPU-programmable logic.

Abstract translation: 本发明的可编程过渡状态机被设计为允许实现能够在预先不知道所需的编码或解码或机器的微处理器环境中增加关键编码和解码任务的性能的硬件。 描述的状态机也可以用于需要灵活性来支持各种功能或机器的系统中，或者硬连线方法无用的系统中。 这种独特的状态机在CPU可编程逻辑中处理状态信息和从当前状态到下一状态的转换。

公开(公告)号：US06918018B2

公开(公告)日：2005-07-12

申请号：US10259309

申请日：2002-09-27

Applicant: Roshan J. Samuel ,  Jason D. Kridner

Inventor： Roshan J. Samuel ,  Jason D. Kridner

IPC: G06F9/38 ,  G06F12/00

CPC classification number: G06F9/383 ,  G06F9/3816 ,  G06F9/3824

Abstract: The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.

Abstract translation: 这里描述的64位单周期提取方法涉及在一系列新的数字信号处理器设备中使用的特定的“巨型”核心处理器。 “巨型”核心将32位内存块整合到单独的实体或银行。 因为父CPU只有三个16位总线，所以通过存储器接口的一个时钟周期的最大读取通常是48位。 本发明描述了一种用于提取方法的方法，该方法包括在存储器接口之前的较早阶段敲击存储体数据。 这允许将正常的48位提取扩展到64位，以满足数字处理器加速器和其他速度关键操作和功能的全面性能。

公开(公告)号：US07062003B2

公开(公告)日：2006-06-13

申请号：US10259158

申请日：2002-09-27

Applicant: Roshan J. Samuel

Inventor： Roshan J. Samuel

IPC: H04L7/00

CPC classification number: H04L7/0331 ,  H04L25/0262

Abstract: The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.

Abstract translation: 本发明描述了一种用于采样数据系统的波特率发生器。 该发生器可以在其波特率未知时对异步数字输入数据进行采样，并且不使用锁相环电路。 本发明使用数字计数器对数字输入数据中连续转换之间的时钟间隔进行计数。 该过程在足以确保数据流中将发生可识别的重复数据模式的时间段内重复。 捕获由计数器记录的最小间隔，并与所需的采样率直接相关。