摘要:
An electronic queue management system for implementation on a chip. The queue management system comprises a plurality of primitive queue elements each including a register for a next-pointer and a register for a queue number. The next-pointer values may be selected via a register input and can be fed out via a registered output. Such queue elements are associated with a respective entry in a central array which stores the data belonging to the actual request. The separation of the data array and queue elements facilitates queue management as the data amounts are quite large compared to the small amount of data being required for the pre logic of the queue management system. Multiple add requests and multiple remove requests operations for different queue elements may be concurrently achieved in a single cycle.
摘要:
A plurality of graphite blocks forms a side reflector with an area of each block that allows a certain amount of radiation induced wear in a predefined zone facing the core of the reactor and an area separate from the wear zone for carrying the load bearing function of the side reflector. Most critical is the area of the upper range of the reactor core where radiation induced wear is greatest. The wear is taken into consideration in the design layout of the side reflector in the form of an increment to the thickness of the wall. The load bearing areas of each block provide the load bearing area for the entire side reflector. The side reflector is particularly suitable for high temperature gas-cooled reactors of the pebble bed type.
摘要:
The invention relates to a method of optimizing a state transition function specification for a state machine engine based on a probability distribution for the state transitions. For the preferred embodiment of the invention, a B-FSM state machine engine accesses a transition rule memory using a processor cache. The invention allows improving the cache hit rate by exploiting the probability distribution. The N transition rules that comprise a hash table entry will be loaded in a burst mode from the main memory, from which the N transition rules are transferred to the processor cache. Because the comparison of the actual state and input values against each of the transition rules can immediately start after each of these rules has been received, the overall performance is improved as the transition rule that is most likely to be selected is the first to be transferred as part of the burst access.
摘要:
The present invention relates to a method, and a respective system, and computer program product for sending data packets along a predefined data path, wherein the receipt of a packet is acknowledged within a predefined time delay that was preset and tuned according to the duration of the send process via said data path. Packets that were sent along the data path are also entered into a pipeline. The pipeline is tuned to have a depth of a predetermined number of clock cycles that correlates to the predefined time delay for the receipt of an acknowledgement message. For a packet in the output registers of the pipeline it is checked if an acknowledge message for the packet was received. Otherwise the packet will be sent again. Especially, the pipeline can be used as a bus trace vehicle.
摘要:
The present invention relates to a method and system for transferring a stream of data from a first higher-speed subsystem of a computer to a plurality of lower speed subsystems, wherein the stream is structured in a sequence of blocks of different bit length, and a block is to be transferred to a specific one of said lower-speed subsystems. A corresponding method uses a queue for buffering the data, which includes control bits [c], [u], [k] to encode the further processing relevant for the association of the data block with a specific one of said lower-speed subsystems, when the queue entry is decoded at the output register of the queue.
摘要:
A non-obtrusive activity monitor is proposed for advantageously monitoring and tracing disjunct, concurrent computer system operations in heavily queued computer systems. For each traced and pending computer system operation, the monitor uses a hardware implementation of an event triggered operation graph to trace the path of the computer system operation through the computer system. For each followed path, a unique signature is generated that significantly reduces the amount of trace data to be stored. In a preferred embodiment, the trace information is stored together with a time stamp for debugging and measuring queuing effects and timing behavior in a computer system.
摘要:
A method and logic circuit for a resource management finite state machine (RM FSM) managing resource(s) required by a protocol FSM. After receiving a resource request vector, the RM FSM determines not all of the required resource(s) are available. The protocol FSM transitions to a new state, generates an output vector, and loads the output vector into an output register. The RM FSM transitions to a state indicating that not all the resources are available and freezes an input register. In a subsequent cycle, the RM FSM freezes the output register and a current state register, and forces the output vector to be seen by the FSM environment as a null token. After determining that the required resource(s) are available, the RM FSM transitions to another state indicating that the resources are available, enables the output vector to be seen by the FSM environment, and unfreezes the protocol FSM.
摘要:
The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.
摘要:
A system and method of implementing multiple programmable finite state machines using a shared transition table is disclosed, the method including forming a plurality of finite state machine cores such that an amount of the plurality of finite state machine cores is unchangeable, forming a state transition array, and forming a routing network such that the forming the plurality of associated state transition elements is realized.
摘要:
Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.