TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS
    1.
    发明申请
    TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS 有权
    使用流动介电材料进行热分解的技术

    公开(公告)号:US20150179501A1

    公开(公告)日:2015-06-25

    申请号:US14139964

    申请日:2013-12-24

    IPC分类号: H01L21/762 H01L29/06

    摘要: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.

    摘要翻译: 公开了用于使用可流动介电材料提供半导体翅片的沟槽隔离的技术。 根据一些实施例,可流动电介质可以例如使用可流动的化学气相沉积(FCVD)工艺沉积在鳍状图案化的半导体衬底上。 可流动电介质可以流入相邻散热片之间的沟槽,其中它可以原位固化,从而根据一些实施例在衬底上形成电介质层。 通过固化,可以根据给定目标应用或最终用途的需要将可流动电介质转化为例如氧化物,氮化物和/或碳化物。 在一些实施例中,所得到的电介质层可以是基本上无缺陷的,没有或以其他方式减少接缝/空隙的量。 在固化之后,所得到的介电层可进行湿化学,热和/或等离子体处理,例如改变其介电特性,密度和/或蚀刻速率中的至少一个。

    HARD MASK ETCH STOP FOR TALL FINS
    2.
    发明申请
    HARD MASK ETCH STOP FOR TALL FINS 有权
    硬盘防火墙防火墙

    公开(公告)号:US20140191300A1

    公开(公告)日:2014-07-10

    申请号:US13997161

    申请日:2011-12-31

    IPC分类号: H01L29/66 H01L29/78

    摘要: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

    摘要翻译: 在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度,并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。 在一个实施例中,使用双硬掩模系统形成硬掩模蚀刻停止件,其中在衬底的表面上形成硬掩模蚀刻停止层,并且使用第二硬掩模层来用硬掩模 在鳍的顶表面上的蚀刻停止层。 去除第二硬掩模层,同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。

    Method of forming a semiconductor device with tall fins and using hard mask etch stops
    3.
    发明授权
    Method of forming a semiconductor device with tall fins and using hard mask etch stops 有权
    用高散热片形成半导体器件并使用硬掩模蚀刻停止件的方法

    公开(公告)号:US09048260B2

    公开(公告)日:2015-06-02

    申请号:US13997161

    申请日:2011-12-31

    摘要: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

    摘要翻译: 在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度,并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。 在一个实施例中,使用双硬掩模系统形成硬掩模蚀刻停止件,其中在衬底的表面上形成硬掩模蚀刻停止层,并且使用第二硬掩模层来用硬掩模 在鳍的顶表面上的蚀刻停止层。 去除第二硬掩模层,同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。