公开(公告)号：US08006204B2

公开(公告)日：2011-08-23

申请号：US11391773

申请日：2006-03-27

申请人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  Dror Eliezer Maydan

发明人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  Dror Eliezer Maydan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F8/20 ,  G06F8/41 ,  G06F8/53 ,  G06F2217/04 ,  G06F2217/68

摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

摘要翻译： 自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器 ，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。 处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。 一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。 通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

公开(公告)号：US07937559B1

公开(公告)日：2011-05-03

申请号：US11761322

申请日：2007-06-11

申请人： Akilesh Parameswar ,  James Alexander Stuart Fiske ,  Ricardo E. Gonzalez

发明人： Akilesh Parameswar ,  James Alexander Stuart Fiske ,  Ricardo E. Gonzalez

IPC分类号： G06F9/00

CPC分类号： G06F9/30149 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3873 ,  G06F9/3885 ,  G06F9/3887

摘要： A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.

摘要翻译： 处理器生成系统包括描述具有三种指令大小的处理器的能力。 在一个示例实现中，指令可以是16位，24位和64位。 这使得可以利用架构中的并行性的新系列架构。 特别地，这使得能够生成VLIW架构。 根据另一方面，处理器生成器允许设计者向处理器添加可配置数量的加载/存储单元。 为了适应多个加载/存储单元，连接到处理器的本地存储器可以具有多个读取和写入端口（每个加载/存储单元一个）。 这进一步允许本地存储器以任何任意连接拓扑连接。 自动生成连接盒硬件，根据配置，在加载/存储单元和本地存储器之间提供接口。

公开(公告)号：US07418575B2

公开(公告)日：2008-08-26

申请号：US11129146

申请日：2005-05-12

申请人： Ricardo E. Gonzalez ,  Scott Johnson ,  Derek Taylor

发明人： Ricardo E. Gonzalez ,  Scott Johnson ,  Derek Taylor

IPC分类号： G06F9/30 ,  G06F7/00

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3897

摘要： A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with at least one of the long instruction word instructions comprising an instruction extension, an extension adapter coupled to the processor and operable to detect the execution of the instruction extension, and programmable logic coupled to the extension adapter and operable to receive configuration data for defining the instruction extension and execute the instruction extension.

摘要翻译： 一种用于向计算机添加可重新配置的计算指令的系统，所述系统包括处理器，所述处理器可操作以执行包括一组计算指令和长指令字指令的计算机程序的指令集，其中所述长指令字指令中的至少一个包括 指令扩展，耦合到所述处理器并且可操作以检测所述指令扩展的执行的扩展适配器，以及耦合到所述扩展适配器的可编程逻辑，并且可操作以接收用于定义所述指令扩展并执行所述指令扩展的配置数据。

公开(公告)号：US06760888B2

公开(公告)日：2004-07-06

申请号：US10286496

申请日：2002-11-01

申请人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  D{grave over (r)}or Eliezer Maydan

发明人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  D{grave over (r)}or Eliezer Maydan

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F8/20 ,  G06F8/41 ,  G06F8/53 ,  G06F2217/04 ,  G06F2217/68

摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

摘要翻译： 自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器 ，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。 处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。 一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。 通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

公开(公告)号：US08161432B2

公开(公告)日：2012-04-17

申请号：US12248890

申请日：2008-10-09

申请人： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

发明人： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC分类号： G06F17/50

CPC分类号： G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

摘要： A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

摘要翻译： 用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。 扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。 该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。 它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。 另外，系统从语言规范生成格式化指令集文档。

公开(公告)号：US07613900B2

公开(公告)日：2009-11-03

申请号：US11021247

申请日：2004-12-21

申请人： Ricardo E. Gonzalez ,  Albert R. Wang

发明人： Ricardo E. Gonzalez ,  Albert R. Wang

IPC分类号： G06F15/00 ,  G06F3/00

CPC分类号： G06F15/17337 ,  G06F15/8023

摘要： An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.

摘要翻译： 具有可选择的输入/输出的集成电路包括被配置为执行指令的第一处理器，被配置为接收和发送标准输入/输出通信的输入/输出接口，配置成处理与第二处理器的处理器间通信的处理器间接口以及选择 电路耦合到输入/输出接口和处理器间接口并被配置为在输入/输出接口和处理器间接口之间进行选择。

公开(公告)号：US07581081B2

公开(公告)日：2009-08-25

申请号：US10750714

申请日：2003-12-31

申请人： Ricardo E. Gonzalez ,  Albert R. Wang ,  Gareld Howard Banta

发明人： Ricardo E. Gonzalez ,  Albert R. Wang ,  Gareld Howard Banta

IPC分类号： G06F15/76

CPC分类号： G06F15/8023 ,  G06F15/17337

摘要： A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the applications. The software extensible device provides additional instructions to a set of standard instructions for the processing element. The communication interface communicates with other processor nodes.

摘要翻译： 用于处理应用的系统包括处理器节点和互连处理器节点的链路。 每个节点包括处理元件，软件可扩展设备和通信接口。 处理元件执行至少一个应用程序。 软件可扩展设备为处理元件的一组标准指令提供附加指令。 通信接口与其他处理器节点进行通信。

公开(公告)号：US20090125866A1

公开(公告)日：2009-05-14

申请号：US12270498

申请日：2008-11-13

申请人： ALBERT REN-RUI WANG ,  RICHARD RUDDELL ,  DAVID WILLIAM GOODWIN ,  EARL A. KILLIAM ,  NUPUR BHATTACHARYYA ,  MARINES PUIG MEDINA ,  WALTER DAVID LICHTENSTEIN ,  PAVLOS KONAS ,  RANGARAJAN SRINIVASAN ,  CHRISTOPHER MARK SONGER ,  AKILESH PARAMESWAR ,  DROR E. MAYDAN ,  RICARDO E. GONZALEZ

发明人： ALBERT REN-RUI WANG ,  RICHARD RUDDELL ,  DAVID WILLIAM GOODWIN ,  EARL A. KILLIAM ,  NUPUR BHATTACHARYYA ,  MARINES PUIG MEDINA ,  WALTER DAVID LICHTENSTEIN ,  PAVLOS KONAS ,  RANGARAJAN SRINIVASAN ,  CHRISTOPHER MARK SONGER ,  AKILESH PARAMESWAR ,  DROR E. MAYDAN ,  RICARDO E. GONZALEZ

IPC分类号： G06F17/50

CPC分类号： G03F7/70466 ,  G03F1/70

摘要： A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

摘要翻译： 一种用于将包含要印刷在晶片上的特征的目标图案分解为多个图案的方法。 该方法包括以下步骤：将目标图案分割成多个贴片; 识别每个补丁内的违反最小间距要求的关键特征; 为具有关键特征的多个补丁中的每一个生成关键组图，其中给定补丁的关键组图定义给定补丁内的关键特征的着色方案，并且关键组图识别延伸到相邻补丁中的关键特征 给给定补丁; 为目标模式生成全局关键组图，其中全局关键组图包括多个补丁中的每一个的关键组图，以及延伸到相邻补丁中的特征的标识; 并基于由全局关键组图定义的着色方案着色目标图案。

公开(公告)号：US20080244471A1

公开(公告)日：2008-10-02

申请号：US12135563

申请日：2008-06-09

申请人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  Dror Eliezer Maydan

发明人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  Dror Eliezer Maydan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F8/20 ,  G06F8/41 ,  G06F8/53 ,  G06F2217/04 ,  G06F2217/68

摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

摘要翻译： 自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器 ，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。 处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。 一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。 通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

公开(公告)号：US06477683B1

公开(公告)日：2002-11-05

申请号：US09246047

申请日：1999-02-05

申请人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  Dror Eliezer Maydan

发明人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson ,  Albert Ren-Rui Wang ,  Dror Eliezer Maydan

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F8/20 ,  G06F8/41 ,  G06F8/53 ,  G06F2217/04 ,  G06F2217/68

摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

摘要翻译： 自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器 ，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。 处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。 一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。 通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。