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公开(公告)号：US20120077551A1
公开(公告)日：2012-03-29
申请号：US13225124
申请日：2011-09-02
IPC分类号： H04B1/38 , H03F1/00 , H01L21/822 , G05F1/10
CPC分类号： H02M3/158 , G05F1/56 , G05F3/242 , G05F3/262 , H01L21/823475 , H01L23/528 , H01L27/0629 , H03F3/189 , H03F3/20 , H04B1/40 , Y10T29/41
摘要： Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.
摘要翻译： 公开了与高电压容限调节器相关的电路和方法。 在一些实施方案中，电压调节器可以被配置为能够处于调节状态和旁路状态。 在调节状态下，可以调节大于所选值的输入电压，以产生所需的输出电压，例如基本恒定的电压。 在旁路状态下，可以调节等于或小于所选值的输入电压，以产生基本上跟踪输入电压的输出电压。 这种在两种模式之间切换的能力可以提供有利的特征，例如降低由于高输入电压引起的电源电路中的损坏的可能性，并且延长诸如可再充电电池的电源的操作持续时间。 还公开了如何在不同的产品和操作和制造方法中实现前述特征的示例。
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公开(公告)号：US09588529B2
公开(公告)日：2017-03-07
申请号：US13225124
申请日：2011-09-02
CPC分类号： H02M3/158 , G05F1/56 , G05F3/242 , G05F3/262 , H01L21/823475 , H01L23/528 , H01L27/0629 , H03F3/189 , H03F3/20 , H04B1/40 , Y10T29/41
摘要： Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.
摘要翻译： 公开了与高电压容限调节器相关的电路和方法。 在一些实施方案中，电压调节器可以被配置为能够处于调节状态和旁路状态。 在调节状态下，可以调节大于所选值的输入电压，以产生所需的输出电压，例如基本恒定的电压。 在旁路状态下，可以调节等于或小于所选值的输入电压，以产生基本上跟踪输入电压的输出电压。 这种在两种模式之间切换的能力可以提供有利的特征，例如降低由于高输入电压引起的电源电路中的损坏的可能性，并且延长诸如可充电电池的电源的操作持续时间。 还公开了如何在不同的产品和操作和制造方法中实现前述特征的示例。
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公开(公告)号：US09083455B2
公开(公告)日：2015-07-14
申请号：US13597693
申请日：2012-08-29
摘要： Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution.
摘要翻译： 在所附权利要求的范围内的射频开关控制器的实现被配置为减少时钟信号引起的杂散的影响。 特别地，这里描述的开关控制器的实施方式包括多相时钟方案，与用于对负电压发生器的电荷泵级进行计时的单相相反。 在一些实施方式中，多相时钟方案减少了时钟信号引起的杂散，并且可能排除了需要额外的片上或片外去耦电容器，这增加了完整的前端模块解决方案的成本和物理尺寸。
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公开(公告)号：US20130052968A1
公开(公告)日：2013-02-28
申请号：US13597693
申请日：2012-08-29
摘要： Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution.
摘要翻译： 在所附权利要求的范围内的射频开关控制器的实现被配置为减少时钟信号引起的杂散的影响。 特别地，这里描述的开关控制器的实施方式包括多相时钟方案，与用于对负电压发生器的电荷泵级进行计时的单相相反。 在一些实施方式中，多相时钟方案减少了时钟信号引起的杂散，并且可能排除了需要额外的片上或片外去耦电容器，这增加了完整的前端模块解决方案的成本和物理尺寸。
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