公开(公告)号：US20120066475A1

公开(公告)日：2012-03-15

申请号：US13298800

申请日：2011-11-17

Applicant: Paulus Stravers ,  Jan-Willem van de Waerdt

Inventor： Paulus Stravers ,  Jan-Willem van de Waerdt

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract translation: 公开了使用RAM和可合成逻辑电路形成的翻译后备缓冲器（TLB）。 TLB提供可合成逻辑内的逻辑，用于将必须搜索的多个存储单元配对以从接收的虚拟地址找到物理地址的转换。 该逻辑提供了用于对接收到的虚拟地址进行散列的散列电路，并使用散列虚拟地址对RAM进行索引，以便在提供翻译的RAM内定位一行。

公开(公告)号：US20080168203A1

公开(公告)日：2008-07-10

申请号：US11817057

申请日：2006-02-21

Applicant: Jayram Moorkanikara Nageswaran ,  Paulus Stravers

Inventor： Jayram Moorkanikara Nageswaran ,  Paulus Stravers

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: The present invention relates to a data processing system comprising a first interrupt controller with an interrupt source interface, an interrupt controller interface, prioritizing means, and an interrupt controller output. The Data processing system further comprises a processing unit providing an interrupt controller interface. The invention also is related to a method for handling interrupt requests. Accordingly, interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller Among said plurality of interrupt requests and said second selected interrupt request a first single interrupt request is selected and transmitted along with a first priority signal, and a first index signal to the processing unit; which initiates an appropriate interrupt service routine on the basis of said first index signal.

Abstract translation: 本发明涉及包括具有中断源接口的第一中断控制器，中断控制器接口，优先化装置和中断控制器输出的数据处理系统。 数据处理系统还包括提供中断控制器接口的处理单元。 本发明还涉及一种处理中断请求的方法。 因此，由第一中断控制器产生的由第一多个中断源产生的中断请求，第二选择的中断请求，第二优先级信号和第二中断源索引信号由第一中断控制器接收。在所述多个中断请求 并且所述第二选择中断请求与第一优先级信号一起选择并发送第一单个中断请求，并将第一索引信号发送到处理单元; 其基于所述第一索引信号启动适当的中断服务程序。

公开(公告)号：US08607026B2

公开(公告)日：2013-12-10

申请号：US13298800

申请日：2011-11-17

Applicant: Paulus Stravers ,  Jan-Willem van de Waerdt

Inventor： Paulus Stravers ,  Jan-Willem van de Waerdt

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract translation: 公开了使用RAM和可合成逻辑电路形成的翻译后备缓冲器（TLB）。 TLB提供可合成逻辑内的逻辑，用于将必须搜索的多个存储单元配对以从接收的虚拟地址找到物理地址的转换。 该逻辑提供了用于对接收到的虚拟地址进行散列的散列电路，并使用散列虚拟地址对RAM进行索引，以便在提供翻译的RAM内定位一行。