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    Semiconductor structure for low parasitic gate capacitance
    2.
    发明授权
    Semiconductor structure for low parasitic gate capacitance 有权
    用于低寄生栅极电容的半导体结构

    公开(公告)号：US07709910B2

    公开(公告)日：2010-05-04

    申请号：US11738666

    申请日：2007-04-23

    申请人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

    发明人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

    摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

    摘要翻译： 半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。 氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平 。 由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。 栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。