公开(公告)号：US07482900B2

公开(公告)日：2009-01-27

申请号：US10556349

申请日：2005-01-25

申请人： Takeshi Hashimoto ,  Noriteru Furumoto ,  Naoki Okumura ,  Hideki Enomoto ,  Takeshi Sadamori ,  Shinichi Kishimoto ,  Tsutomu Shimomura ,  Kouji Sakai ,  Masami Hori

发明人： Takeshi Hashimoto ,  Noriteru Furumoto ,  Naoki Okumura ,  Hideki Enomoto ,  Takeshi Sadamori ,  Shinichi Kishimoto ,  Tsutomu Shimomura ,  Kouji Sakai ,  Masami Hori

IPC分类号： H01H67/02

CPC分类号： H01H50/005 ,  H01H2050/007

摘要： The micro relay of the present invention comprises a base substrate 3, an armature block 5, and a cover 7. The base substrate 3 has a storage recess 41 for accommodating an electromagnetic device 1. The storage recess is composed of a hole 41a penetrating the base substrate 3 and a thin storage recess lid fixed on the one surface of the base substrate to close the hole. The electromagnetic device 1 is isolated from a contact mechanism by the storage recess lid 41b to increase the reliability of the contacts. The electromagnetic device 1 includes a yoke 10, a coil 11 wound around the yoke to generate a flux in response to an exciting current, and a permanent magnet 12 secured to the yoke to generate a flux flowing through an armature 51 and the yoke 10. Because the permanent magnet 12 is secured to the yoke 10, this micro relay can reduce the thickness.

摘要翻译： 本发明的微型继电器包括基底基板3，电枢块5和盖7.基底基板3具有用于容纳电磁装置1的储存凹部41.储存凹部由贯穿 基底基板3和固定在基底基板的一个表面上的薄的储存凹部盖以封闭孔。 电磁装置1通过存储凹部盖41b与接触机构隔离，以提高触点的可靠性。 电磁装置1包括磁轭10，卷绕在磁轭上以产生响应于励磁电流的磁通的线圈11和固定到磁轭的永磁体12，以产生流过电枢51和磁轭10的磁通。 因为永磁体12被固定到磁轭10上，所以这个微型继电器可以减小厚度。

公开(公告)号：US20060250201A1

公开(公告)日：2006-11-09

申请号：US10556349

申请日：2005-01-25

申请人： Takeshi Hashimoto ,  Noriteru Furumoto ,  Naoki Okumura ,  Hideki Enomoto ,  Takeshi Sadamori ,  Shinichi Kishimoto ,  Tsutomu Shimomura ,  Kouji Sakai ,  Masami Hori

发明人： Takeshi Hashimoto ,  Noriteru Furumoto ,  Naoki Okumura ,  Hideki Enomoto ,  Takeshi Sadamori ,  Shinichi Kishimoto ,  Tsutomu Shimomura ,  Kouji Sakai ,  Masami Hori

IPC分类号： H01H51/22

CPC分类号： H01H50/005 ,  H01H2050/007

摘要： The micro relay of the present invention comprises a base substrate 3, an armature block 5, and a cover 7. The base substrate 3 has a storage recess 41 for accommodating an electromagnetic device 1. The storage recess is composed of a hole 41a penetrating the base substrate 3 and a thin storage recess lid fixed on the one surface of the base substrate to close the hole. The electromagnetic device 1 is isolated from a contact mechanism by the storage recess lid 41b to increase the reliability of the contacts. The electromagnetic device 1 includes a yoke 10, a coil 11 wound around the yoke to generate a flux in response to an exciting current, and a permanent magnet 12 secured to the yoke to generate a flux flowing through an armature 51 and the yoke 10. Because the permanent magnet 12 is secured to the yoke 10, this micro relay can reduce the thickness.

摘要翻译： 本发明的微型继电器包括基底基板3，电枢块5和盖7.基底基底3具有用于容纳电磁装置1的储存凹部41.储存凹部由孔41穿透 基底基板3和固定在基底基板的一个表面上的薄的储存凹部盖以封闭孔。 电磁装置1通过存储凹部盖41b与接触机构隔离，以提高触点的可靠性。 电磁装置1包括磁轭10，卷绕在磁轭上以产生响应于励磁电流的磁通的线圈11和固定到磁轭的永磁体12，以产生流过电枢51和磁轭10的磁通。 因为永磁体12被固定到磁轭10上，所以这个微型继电器可以减小厚度。

公开(公告)号：US5278422A

公开(公告)日：1994-01-11

申请号：US935413

申请日：1992-08-26

申请人： Fumio Kato ,  Sigeo Akiyama ,  Masahiro Izumi ,  Noriteru Furumoto

发明人： Fumio Kato ,  Sigeo Akiyama ,  Masahiro Izumi ,  Noriteru Furumoto

IPC分类号： H03K17/0412 ,  H03K17/16 ,  H03K17/785 ,  G02B27/00 ,  H03K3/42

CPC分类号： H03K17/163 ,  H03K17/04123 ,  H03K17/785

摘要： A solid state relay circuit includes a MOSFET receiving a photovoltaic output generated across a photovoltaic diode array responsive to a light signal from a light emitting element, a control electrode of a normally ON type driving transistor made to be at a high impedance state by a voltage generated across an impedance element connected in series to the photovoltaic diode array upon application of the photovoltaic output across the gate and source of the MOSFET and at a low impedance state upon disappearance of the photovoltaic output is connected to a connecting point between the diode array and the impedance element, and the driving transistor is connected across the gate and source of the MOSFET with a resistor interposed. A falling gradient of output signal upon being turned OFF of the relay circuit is made thereby sufficiently gentle, and relay operation upon being turned OFF can be minimized in response time.

摘要翻译： 固态继电器电路包括：MOSFET接收光电二极管阵列产生的光电输出，该光伏输出响应于来自发光元件的光信号，正常导通型驱动晶体管的控制电极被制成处于高阻抗状态的电压 在跨越MOSFET的栅极和源极施加光伏输出并且在光伏输出消失时处于低阻抗状态的阻抗元件上串联连接到光伏二极管阵列的阻抗元件连接到二极管阵列和 阻抗元件和驱动晶体管连接在MOSFET的栅极和源极之间，并插入电阻器。 使继电器电路断开时的输出信号的下降斜率足够平缓，并且在关断时的继电器动作可以在响应时间内最小化。

公开(公告)号：US06930870B2

公开(公告)日：2005-08-16

申请号：US10380171

申请日：2001-09-27

申请人： Takeshi Nobe ,  Shigeo Akiyama ,  Noriteru Furumoto ,  Takuya Sunada

发明人： Takeshi Nobe ,  Shigeo Akiyama ,  Noriteru Furumoto ,  Takuya Sunada

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K17/00 ,  H03K17/08 ,  H03K17/082 ,  H03K17/785 ,  H02H5/00

CPC分类号： H03K17/785 ,  H01L27/0251 ,  H01L27/0266 ,  H01L2924/0002 ,  H03K17/0822 ,  H03K2017/0806 ,  H01L2924/00

摘要： The semiconductor device is inserted between a power source and a load. A current flowing between an external drain terminal D and an external source terminal S is controlled in accordance with a control voltage applied between an external gate terminal G and the external source terminal S. In addition, the semiconductor device has a main MOSFET 1 and a detecting MOSFET 2 each of which is inserted between the external drain terminal D and the external source terminal S, a protective circuit 3 which protects the main MOSFET 1 by a protective transistor 5 when the abnormality is detected thereby, and an impedance element 4 inserted between the protective MOSFET 5, and a junction connecting the external gate terminal G to a gate electrode of the detecting MOSFET 2.

摘要翻译： 半导体器件插入电源和负载之间。 根据施加在外部栅极端子G和外部源极端子S之间的控制电压来控制在外部漏极端子D和外部源极端子S之间流动的电流。另外，半导体器件具有主MOSFET 1和 检测MOSFET 2，其插入在外部漏极端子D和外部源极端子S之间;保护电路3，其在检测到异常时由保护晶体管5保护主MOSFET 1;以及阻抗元件4，其插入在 保护MOSFET5以及将外部栅极端子G连接到检测用MOSFET2的栅电极的结。