DATA TRANSFER CIRCUIT AND COMMUNICATION APPARATUS

    公开(公告)号:US20230216653A1

    公开(公告)日:2023-07-06

    申请号:US18000621

    申请日:2021-05-27

    IPC分类号: H04L7/00

    CPC分类号: H04L7/0016

    摘要: A data transfer circuit (40) according to the invention includes a memory (41) configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit (44) configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit (42) configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit (43) configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit (44) generates the second clock by multiplying the reference clock by a rational number (N+ΔN) using the adjustment multiple ΔN output from the adjustment circuit (43). A data transfer circuit capable of speeding up clock synchronization can be provided.

    Arithmetic circuit for performing product-sum arithmetic

    公开(公告)号:US11494165B2

    公开(公告)日:2022-11-08

    申请号:US16959986

    申请日:2018-12-18

    IPC分类号: G06F7/544 G06F7/53

    摘要: An arithmetic circuit includes a LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] that are sums of products of data x[m, n] of a data set X[m] containing M pairs of data x[m, n] and the coefficients c[n], in parallel for each of the M pairs. The distributed arithmetic circuit (2-m) includes binomial distributed arithmetic circuits that, for each of the pairs, calculate sums of products of a value obtained by pairing N data x[m, n] corresponding to the circuit two by two and a value obtained by pairing the coefficients c[n] two by two, and a figure matching circuit that matches a number of decimal figures of the sums with a predetermined number of decimal figures.

    Optical module
    5.
    发明授权

    公开(公告)号:US11333950B2

    公开(公告)日:2022-05-17

    申请号:US17295669

    申请日:2019-08-30

    摘要: An optical module of a configuration that ensures use of commercially available electronic components and reduction of the number of current generation circuits and electric wirings. The optical module includes an electronic component mounted on a separate board from a light wave circuit board provided with an optical component such as an optical switch, and they are each electrically connected by wire bonding. For this reason, the optical module can use a commercially available electronic component. In addition, the module has a configuration in which heaters of optical switches, which do not simultaneously flow currents, are grouped and a current from one current generation circuit is supplied to any one of the heaters in the group by means of one electrical switch. For this reason, the optical module does not have to be prepared with the same number of electrical switches and current generation circuits as the number of heaters.

    Multicast switch
    6.
    发明授权

    公开(公告)号:US11287578B2

    公开(公告)日:2022-03-29

    申请号:US16982491

    申请日:2019-03-26

    IPC分类号: G02B6/35 G02B6/12 G02F1/313

    摘要: There is provided a small MCS with the number of leads reduced by half as compared with the conventional configuration. A multicast switch according to the present invention is formed on a substrate, comprising: M input ports, N output ports; M×N optical switch units (optical SU); optical waveguides optically connecting the M input ports, M×N optical SU, and N output ports; and leads connected to the respective M×N optical SU. A multicast switch is configured such that by activating one optical SU, an optical signal input to an input port associated with the activated optical SU is output from an output port associated with the activated optical SU. The M×N optical SU include at least a gate switch and a main switch. In each optical SU, the gate switch and the main switch are connected to the common lead.

    OPTICAL MODULE
    7.
    发明申请

    公开(公告)号:US20220019030A1

    公开(公告)日:2022-01-20

    申请号:US17295669

    申请日:2019-08-30

    IPC分类号: G02B6/35

    摘要: An optical module of a configuration that ensures use of commercially available electronic components and reduction of the number of current generation circuits and electric wirings. The optical module includes an electronic component mounted on a separate board from a light wave circuit board provided with an optical component such as an optical switch, and they are each electrically connected by wire bonding. For this reason, the optical module can use a commercially available electronic component. In addition, the module has a configuration in which heaters of optical switches, which do not simultaneously flow currents, are grouped and a current from one current generation circuit is supplied to any one of the heaters in the group by means of one electrical switch. For this reason, the optical module does not have to be prepared with the same number of electrical switches and current generation circuits as the number of heaters.

    ADAPTIVE EQUALIZATION DEVICE, ADAPTIVE EQUALIZATION METHOD, AND COMMUNICATION DEVICE

    公开(公告)号:US20210344424A1

    公开(公告)日:2021-11-04

    申请号:US17273544

    申请日:2019-10-07

    IPC分类号: H04B10/2569 H04B10/61

    摘要: First compensation circuitry includes a first digital filter compensating a phase difference between a phase of a symbol of a received signal and a sampling timing, and first filter coefficient calculation circuitry calculating a filter coefficient of the first digital filter as a first filter coefficient. Second filter coefficient calculation circuitry calculates, as a second filter coefficient, a filter coefficient for adaptive equalization that compensates distortion due to temporally changing polarization dispersion, based on an output of the first digital filter. Coefficient combination circuitry combines the first filter coefficient and the second filter coefficient. Second compensation circuitry includes a second digital filter which uses a filter coefficient combined by the coefficient combination circuitry and performs a compensation of the phase difference between the phase of the symbol of the received signal and the sampling timing, and a process of the adaptive equalization at the same time.