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    Performance in predicting branches
    1.
    发明授权
    Performance in predicting branches 有权
    在预测分支中的表现

    公开(公告)号：US08972706B2

    公开(公告)日：2015-03-03

    申请号：US13116515

    申请日：2011-05-26

    Applicant: Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

    Inventor： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

    IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38

    CPC classification number: G06F9/3844 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

    Abstract: A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

    Abstract translation: 用于处理指令的数据处理系统和计算机程序产品。 所述指令由处理器单元处理，同时使用多个表中的第一表来预测在处理条件指令之后所述处理器单元所需的一组指令。 形成识别，即当使用第一表时正确预测指令集的成功率小于阈值数。 搜索由处理器单元处理的指令的序列，以搜索与用于识别何时使用多个表的一组标记中的标记相匹配的指令。 形成与标记相符的指令的标识。 识别由标记引用的多个表中的第二表。 第二个表用于代替第一个表。

    VARIABLE CACHE LINE SIZE MANAGEMENT
    3.
    发明申请
    VARIABLE CACHE LINE SIZE MANAGEMENT 有权
    可变缓存线尺寸管理

    公开(公告)号：US20130111135A1

    公开(公告)日：2013-05-02

    申请号：US13286507

    申请日：2011-11-01

    Applicant: Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    Inventor： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    IPC: G06F12/08

    CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0897

    Abstract: According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

    Abstract translation: 根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。 该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小 对应于较低级别缓存的高速缓存行大小。 该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

    Synchronizing access to a shared resource utilizing selective locking
    4.
    发明授权
    Synchronizing access to a shared resource utilizing selective locking 有权
    使用选择性锁定同步访问共享资源

    公开(公告)号：US08225327B2

    公开(公告)日：2012-07-17

    申请号：US11227032

    申请日：2005-09-15

    Applicant: David W. Mehaffy ,  Greg R. Mewhinney ,  Mysore S. Srinivas

    Inventor： David W. Mehaffy ,  Greg R. Mewhinney ,  Mysore S. Srinivas

    IPC: G06F9/46 ,  G06F9/45 ,  G06F17/00

    CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/544

    Abstract: A method and system for providing access to a shared resource utilizing selective locking are disclosed. According to one embodiment, a method is provided comprising receiving a request to perform a resource access operation on a shared resource, invoking a first routine to perform the resource access operation, detecting a data processing system exception generated in response to invoking the first routine, and invoking a second routine to perform the resource access operation in response to such detecting. In the described embodiment, the first routine comprises a dereference instruction to dereference a pointer to memory associated with the shared resource, the second routine comprises a lock acquisition instruction to acquire a global lock associated with the shared resource prior to a performance of the resource access operation and a lock release instruction to release the global lock once resource access operation has been performed.

    Abstract translation: 公开了一种利用选择性锁定来提供对共享资源的访问的方法和系统。 根据一个实施例，提供了一种方法，包括接收对共享资源执行资源访问操作的请求，调用第一例程以执行资源访问操作，检测响应于调用第一例程而生成的数据处理系统异常， 并且响应于这种检测，调用第二例程来执行资源访问操作。 在所描述的实施例中，第一例程包括取消引用指令以取消对与共享资源相关联的存储器的指针的引用，第二例程包括在执行资源访问之前获取与共享资源相关联的全局锁定的锁获取指令 一旦执行资源访问操作，操作和锁定释放指令释放全局锁定。

    Programmable Data Prefetching
    5.
    发明申请
    Programmable Data Prefetching 有权
    可编程数据预取

    公开(公告)号：US20080256302A1

    公开(公告)日：2008-10-16

    申请号：US11733352

    申请日：2007-04-10

    Applicant: William A. Maron ,  Greg R. Mewhinney ,  Mysore S. Srinivas ,  David B. Whitworth

    Inventor： William A. Maron ,  Greg R. Mewhinney ,  Mysore S. Srinivas ,  David B. Whitworth

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F2212/6028

    Abstract: A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.

    Abstract translation: 提供了一种用于将数据预取到高速缓冲存储器中的方法，计算机程序产品和系统。 当执行程序时，获得程序的第一对象的对象标识符。 对数据结构执行查找操作以确定对象标识符是否存在于数据结构中。 响应于数据结构中存在的对象标识符，检索由对象标识符引用的引用对象标识符。 然后，与被引用的对象标识符相关联的数据从主存储器预取到高速缓冲存储器中。

    Dynamically assigning a portion of physical computing resource to logical partitions based on characteristics of executing logical partitions
    7.
    发明授权
    Dynamically assigning a portion of physical computing resource to logical partitions based on characteristics of executing logical partitions 有权
    基于执行逻辑分区的特性，将物理计算资源的一部分动态地分配给逻辑分区

    公开(公告)号：US09135080B2

    公开(公告)日：2015-09-15

    申请号：US13460448

    申请日：2012-04-30

    Applicant: Diane G. Flemming ,  Octavian F. Herescu ,  William A. Maron ,  Mysore S. Srinivas

    Inventor： Diane G. Flemming ,  Octavian F. Herescu ,  William A. Maron ,  Mysore S. Srinivas

    IPC: G06F9/46 ,  G06F9/50 ,  G06F9/455

    CPC classification number: G06F9/5011 ,  G06F9/45516 ,  G06F9/45558 ,  G06F9/4881 ,  G06F9/5088 ,  G06F2009/4557 ,  G06F2009/45579

    Abstract: A computer implemented method includes determining first characteristics of a first logical partition, the first characteristics including a memory footprint characteristic. The method includes assigning a first portion of a first set of physical computing resources to the first logical partition. The first set of physical computing resources includes a plurality of processors that includes a first processor having a first processor type and a second processor having a second processor type. The first portion includes the second processor. The method includes dispatching the first logical partition to execute using the first portion. The method includes creating a second logical partition that includes the second processor and assigning a second portion of the first set of physical computing resources to the second logical partition. The method includes dispatching the second logical partition to execute using the second portion.

    Abstract translation: 计算机实现的方法包括确定第一逻辑分区的第一特征，所述第一特征包括存储器占用特征。 该方法包括将第一组物理计算资源的第一部分分配给第一逻辑分区。 第一组物理计算资源包括多个处理器，其包括具有第一处理器类型的第一处理器和具有第二处理器类型的第二处理器。 第一部分包括第二处理器。 该方法包括使用第一部分调度第一逻辑分区以执行。 该方法包括创建包括第二处理器并将第一组物理计算资源的第二部分分配给第二逻辑分区的第二逻辑分区。 该方法包括使用第二部分调度第二逻辑分区以执行。

    Variable cache line size management
    8.
    发明授权
    Variable cache line size management 有权
    可变缓存行大小管理

    公开(公告)号：US08943272B2

    公开(公告)日：2015-01-27

    申请号：US13451742

    申请日：2012-04-20

    Applicant: Robert H. Bell, Jr. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    Inventor： Robert H. Bell, Jr. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0897

    Abstract: According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.

    Abstract translation: 根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。 该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行 对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

    Dynamic prioritization of cache access
    9.
    发明授权
    Dynamic prioritization of cache access 有权
    高速缓存访​​问的动态优先级

    公开(公告)号：US08769210B2

    公开(公告)日：2014-07-01

    申请号：US13323076

    申请日：2011-12-12

    Applicant: Robert H. Bell, Jr. ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    Inventor： Robert H. Bell, Jr. ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    IPC: G06F12/08

    CPC classification number: G06F12/0815

    Abstract: Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an amount of cache resources used to service cache misses within a past period. In some embodiments, each of the cache state machines is configured to, determine whether a memory access request results in a cache miss or cache hit, and in response to a cache miss for a memory access request, query the tracking unit for the amount of cache resources used to service cache misses within the past period. In some embodiments, the each of the cache state machines is configured to service the memory access request based, at least in part, on the amount of cache resources used to service the cache misses within the past period according to the tracking unit.

    Abstract translation: 本发明主题的一些实施例涉及包括跟踪单元和高速缓存状态机的高速缓存。 在一些实施例中，跟踪单元被配置为跟踪用于在过去时间段内服务高速缓存未命中的高速缓存资源的量。 在一些实施例中，每个高速缓存状态机被配置为，确定存储器访问请求是否导致高速缓存未命中或高速缓存命中，并且响应于存储器访问请求的高速缓存未命中，查询跟踪单元的数量 用于在过去一段时间内缓存未命中服务的缓存资源。 在一些实施例中，每个高速缓存状态机被配置为至少部分地基于用于根据跟踪单元在过去时段内服务高速缓存未命中的高速缓存资源的量来服务存储器访问请求。

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