-
公开(公告)号：US20130299977A1
公开(公告)日：2013-11-14
申请号：US13468891
申请日：2012-05-10
IPC分类号： H01L23/498 , H01L23/488
CPC分类号： H01L25/0652 , H01L24/05 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/73203 , H01L2224/73253 , H01L2224/81123 , H01L2224/81129 , H01L2225/06517 , H01L2225/06562 , H01L2225/06568 , H01L2225/06579 , H01L2924/00014 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.
摘要翻译： 芯片封装包括彼此偏移的半导体管芯或芯片的堆叠，从而限定具有暴露焊盘的露台。 此外，阶梯式台阶中的每个半导体管芯的表面包括大致平行于半导体管芯的边缘的两排第一焊盘。 此外，芯片封装包括大致平行于平台的高带宽斜坡部件，并且具有包括布置在用于每个半导体管芯的至少两行第二焊盘中的第二焊盘的表面。 第二焊盘通过连接器电连接和机械耦合到暴露的第一焊盘。 因此，芯片封装中的电触点可以具有导电性，电容性或通常的复阻抗。 此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。
-
公开(公告)号：US09082632B2
公开(公告)日：2015-07-14
申请号：US13468891
申请日：2012-05-10
CPC分类号： H01L25/0652 , H01L24/05 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/73203 , H01L2224/73253 , H01L2224/81123 , H01L2224/81129 , H01L2225/06517 , H01L2225/06562 , H01L2225/06568 , H01L2225/06579 , H01L2924/00014 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.
摘要翻译： 芯片封装包括彼此偏移的半导体管芯或芯片的堆叠，从而限定具有暴露焊盘的露台。 此外，阶梯式台阶中的每个半导体管芯的表面包括大致平行于半导体管芯的边缘的两排第一焊盘。 此外，芯片封装包括大致平行于平台的高带宽斜坡部件，并且具有包括布置在用于每个半导体管芯的至少两行第二焊盘中的第二焊盘的表面。 第二焊盘通过连接器电连接和机械耦合到暴露的第一焊盘。 因此，芯片封装中的电触点可以具有导电性，电容性或通常的复阻抗。 此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。
-
搜索结果
2 条记录 (耗时 0.011 秒)
