公开(公告)号：US08711927B2

公开(公告)日：2014-04-29

申请号：US12636321

申请日：2009-12-11

申请人： Megha Agarwal ,  Sumit Johar ,  Kaushik Saha ,  Emiliano Mario Piccinelli

发明人： Megha Agarwal ,  Sumit Johar ,  Kaushik Saha ,  Emiliano Mario Piccinelli

IPC分类号： H04N7/26

CPC分类号： H04N19/48 ,  H04N19/115 ,  H04N19/149 ,  H04N19/152 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61

摘要： An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

摘要翻译： 本公开的实施例涉及一种包括编码装置的系统。 所述编码装置包括压缩单元，量化器，比特估计器，比特率编码器和可变长度编码器。 实施例也是一种编码方法。 所述方法估计在压缩数据流之后编码宏块的位数。 然后估计比特由比特率编码器编码并由量化器进一步量化以获得最终的编码比特流。 在量化处理之后和编码处理之前估计编码宏块所需的位数。 宏块比特估计器根据该宏块的量化AC系数和在宏块级标准化的相邻帧的量化AC系数来估计对特定宏块进行编码所需的比特数。

公开(公告)号：US08665948B2

公开(公告)日：2014-03-04

申请号：US12275947

申请日：2008-11-21

申请人： Megha Agarwal ,  Sumit Johar ,  Saha Kaushik ,  Emiliano Mario Piccinelli

发明人： Megha Agarwal ,  Sumit Johar ,  Saha Kaushik ,  Emiliano Mario Piccinelli

IPC分类号： H04N7/12 ,  H04N11/12

CPC分类号： H04N19/40 ,  H04N19/115 ,  H04N19/149 ,  H04N19/196 ,  H04N19/61

摘要： Rate control algorithms are adapted to cover multiple encoding standards. A rate controller includes an input adaptation interface, a core rate controller, and an output adaptation interface. The input adaptation interface converts rate control input parameters of a target encoding standard to corresponding native control input parameters of the rate controller. The core rate controller is coupled to the output of the input adaptation interface generating output parameters conforming to its native encoding standard. The output adaptation interface is coupled to the output of the core rate controller converting the generated output parameters to equivalent rate control output parameters conforming to the target encoding standard.

摘要翻译： 速率控制算法适用于覆盖多种编码标准。 速率控制器包括输入适配接口，核心速率控制器和输出适配接口。 输入自适应接口将目标编码标准的速率控制输入参数转换为速率控制器的相应本机控制输入参数。 核心速率控制器耦合到输入自适应接口的输出，产生符合其天然编码标准的输出参数。 输出适配接口耦合到核心速率控制器的输出，将所生成的输出参数转换为符合目标编码标准的等效速率控制输出参数。

公开(公告)号：US20100158108A1

公开(公告)日：2010-06-24

申请号：US12636321

申请日：2009-12-11

申请人： Megha AGARWAL ,  Sumit JOHAR ,  Kaushik SAHA ,  Emiliano Mario Piccinelli

发明人： Megha AGARWAL ,  Sumit JOHAR ,  Kaushik SAHA ,  Emiliano Mario Piccinelli

IPC分类号： H04N7/26

CPC分类号： H04N19/48 ,  H04N19/115 ,  H04N19/149 ,  H04N19/152 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61

摘要： An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

摘要翻译： 本公开的实施例涉及一种包括编码装置的系统。 所述编码装置包括压缩单元，量化器，比特估计器，比特率编码器和可变长度编码器。 实施例也是一种编码方法。 所述方法估计在压缩数据流之后编码宏块的位数。 然后估计比特由比特率编码器编码并由量化器进一步量化以获得最终的编码比特流。 在量化处理之后和编码处理之前估计编码宏块所需的位数。 宏块比特估计器根据该宏块的量化AC系数和在宏块级标准化的相邻帧的量化AC系数来估计对特定宏块进行编码所需的比特数。

公开(公告)号：US20090154558A1

公开(公告)日：2009-06-18

申请号：US12275947

申请日：2008-11-21

申请人： Megha Agarwal ,  Sumit Johar ,  Saha Kaushik ,  Emiliano Mario Piccinelli

发明人： Megha Agarwal ,  Sumit Johar ,  Saha Kaushik ,  Emiliano Mario Piccinelli

IPC分类号： H04N7/26

CPC分类号： H04N19/40 ,  H04N19/115 ,  H04N19/149 ,  H04N19/196 ,  H04N19/61

摘要： Rate control algorithms are adapted to cover multiple encoding standards are described. A rate controller includes an input adaptation interface, a core rate controller, and an output adaptation interface. The input adaptation interface converts rate control input parameters of a target encoding standard to corresponding native control input parameters of the rate controller. The core rate controller is coupled to the output of the input adaptation interface generating output parameters conforming to its native encoding standard. The output adaptation interface is coupled to the output of the core rate controller converting the generated output parameters to equivalent rate control output parameters conforming to the target encoding standard.

摘要翻译： 速率控制算法适用于覆盖多种编码标准。 速率控制器包括输入适配接口，核心速率控制器和输出适配接口。 输入自适应接口将目标编码标准的速率控制输入参数转换为速率控制器的相应本机控制输入参数。 核心速率控制器耦合到输入自适应接口的输出，产生符合其天然编码标准的输出参数。 输出适配接口耦合到核心速率控制器的输出，将所生成的输出参数转换为符合目标编码标准的等效速率控制输出参数。