公开(公告)号：US08520958B2

公开(公告)日：2013-08-27

申请号：US12702497

申请日：2010-02-09

Applicant: Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

Inventor： Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

IPC: G06K9/36

CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

公开(公告)号：US08456197B2

公开(公告)日：2013-06-04

申请号：US13118858

申请日：2011-05-31

Applicant: Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

Inventor： Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC classification number: G11C7/065 ,  H04L25/0274

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract translation: 第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。 第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。 每个感测电路具有真实的信号感测路径和互补信号感测路径。 第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。 来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。

公开(公告)号：US08624623B2

公开(公告)日：2014-01-07

申请号：US13340674

申请日：2011-12-30

Applicant: Navneet Gupta ,  Prashant Dubey ,  Kaushik Saha ,  AtulKumar Kashyap

Inventor： Navneet Gupta ,  Prashant Dubey ,  Kaushik Saha ,  AtulKumar Kashyap

IPC: H03K19/003 ,  H03K19/173

CPC classification number: H03K3/356156 ,  H03K3/0375

Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.

Abstract translation: 根据实施例，一种装置包括：被配置为接收数据锁存器的数据输入信号的第一节点; 第二节点，被配置为接收数据锁存器的数据输出信号; 处理和保持电路，被配置为处理在第一节点处接收的数据输入信号的值与在第二节点处接收到的数据输出信号的值之间的差异，并响应于该差异保持第一和第二节点处的相应值; 以及比较电路，被配置为比较在第一节点处保持的值和数据锁存器的数据输出信号的值; 其中所述处理和保持电路被配置为朝向在所述第一节点和所述第二节点之一处接收的信号偏置。

公开(公告)号：US08587292B2

公开(公告)日：2013-11-19

申请号：US12842256

申请日：2010-07-23

Applicant: Surinder Pal Singh ,  Kaushik Saha

Inventor： Surinder Pal Singh ,  Kaushik Saha

IPC: G01R1/20

CPC classification number: H04L67/025 ,  G01R19/22 ,  G01R21/133 ,  H04L41/32

Abstract: A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

公开(公告)号：US20130169360A1

公开(公告)日：2013-07-04

申请号：US13340674

申请日：2011-12-30

Applicant: Navneet GUPTA ,  Prashant DUBEY ,  Kaushik SAHA ,  AtulKumar KASHYAP

Inventor： Navneet GUPTA ,  Prashant DUBEY ,  Kaushik SAHA ,  AtulKumar KASHYAP

IPC: H03F3/45 ,  H03K19/003

CPC classification number: H03K3/356156 ,  H03K3/0375

Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.

Abstract translation: 根据实施例，一种装置包括：被配置为接收数据锁存器的数据输入信号的第一节点; 第二节点，被配置为接收数据锁存器的数据输出信号; 处理和保持电路，被配置为处理在第一节点处接收的数据输入信号的值与在第二节点处接收到的数据输出信号的值之间的差异，并响应于该差异保持第一和第二节点处的相应值; 以及比较电路，被配置为比较在第一节点处保持的值和数据锁存器的数据输出信号的值; 其中所述处理和保持电路被配置为朝向在所述第一节点和所述第二节点之一处接收的信号偏置。

公开(公告)号：US07870177B2

公开(公告)日：2011-01-11

申请号：US10781336

申请日：2004-02-17

Applicant: Kaushik Saha ,  Srijib Narayan

Inventor： Kaushik Saha ,  Srijib Narayan

IPC: G06F15/00

CPC classification number: G06F17/142

Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor. The embodiments of the invention also provide a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements.

Abstract translation: 本发明的实施例提供了一种用于在多处理器架构中实现FFT / IFFT计算的可扩展方法，其通过在使用“P”处理的实现的第一“log2P”阶段的计算之后消除对处理器间通信的需要来提供改进的吞吐量 元素，包括同时在单个处理器或每个“P”处理器上计算第一“log2P”阶段的每个蝴蝶并在“P”个处理器中的所有后续阶段中分配蝴蝶的计算，使得每个链 由具有连接在一起的输入和输出的蝴蝶组成的级联蝴蝶由相同的处理器处理。 本发明的实施例还提供了一种用于在多处理器架构中获得FFT / IFFT计算的可伸缩实现的系统，其通过在使用“P”的实现的计​​算第一“log2P”阶段之后消除对处理器间通信的需要而提供改进的吞吐量 “处理要素

公开(公告)号：US20090265739A1

公开(公告)日：2009-10-22

申请号：US12105834

申请日：2008-04-18

Applicant: Prabhjot Singh ARORA ,  Kaushik Saha

Inventor： Prabhjot Singh ARORA ,  Kaushik Saha

IPC: H04N5/445 ,  G06F13/00 ,  H04N7/173

CPC classification number: H04N7/163 ,  H04N5/44543 ,  H04N5/44591 ,  H04N21/4345 ,  H04N21/4384 ,  H04N21/4438 ,  H04N21/4755 ,  H04N21/482

Abstract: The present invention discloses a system and method for channel selection in a digital broadcast reception terminal. The system tunes to different frequencies and generates visual clips corresponding to a plurality of channels in a frequency band. Visual clips of multiple channels are simultaneously displayed on a display screen which provides the user an easy way to select a desired program.

Abstract translation: 本发明公开了一种在数字广播接收终端中进行频道选择的系统和方法。 该系统调谐到不同的频率并产生与频带中的多个信道相对应的视频剪辑。 多个频道的视频剪辑同时显示在显示屏幕上，为用户提供了一种选择所需节目的简单方法。

公开(公告)号：US20090103622A1

公开(公告)日：2009-04-23

申请号：US12253062

申请日：2008-10-16

Applicant: Subarna Tripathi ,  Kaushik Saha ,  Emiliana Picinelli

Inventor： Subarna Tripathi ,  Kaushik Saha ,  Emiliana Picinelli

IPC: H04N7/26

CPC classification number: H04N19/59 ,  H04N19/103 ,  H04N19/176 ,  H04N19/196 ,  H04N19/40

Abstract: A system and corresponding method determines a macroblock partition to transcode digital data from a first video standard to a second video standard with any spatial resolution. The system includes a processing module and an encoding module. The processing module processes digital data to determine a macroblock partition. The encoding module is coupled to the processing module for encoding the digital data based on the macroblock partition. The system is further coupled to a decoding module for receiving the digital data. The method determines the partition of a macroblock for transcoding digital data with any spatial resolution and without any motion estimation.

Abstract translation: 系统和相应的方法确定宏块分区以将数字数据从第一视频标准转码为具有任何空间分辨率的第二视频标准。 该系统包括处理模块和编码模块。 处理模块处理数字数据以确定宏块分区。 编码模块耦合到处理模块，用于基于宏块分区对数字数据进行编码。 该系统进一步耦合到用于接收数字数据的解码模块。 该方法确定用于使用任何空间分辨率对数字数据进行代码转换并且没有任何运动估计的宏块的分区。

公开(公告)号：US20110291642A1

公开(公告)日：2011-12-01

申请号：US12842256

申请日：2010-07-23

Applicant: Surinder Pal SINGH ,  Kaushik SAHA

Inventor： Surinder Pal SINGH ,  Kaushik SAHA

IPC: G01R1/20

CPC classification number: H04L67/025 ,  G01R19/22 ,  G01R21/133 ,  H04L41/32

Abstract: A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

Abstract translation: 电子设备中的功率测量系统包括感测单元，模数转换器（ADC）和控制器。 感测单元感测电源两端的电压，并根据检测到的电压调制载波信号。 ADC转换由电子设备接收的调制载波信号和音频信号的组合，以生成数字化的组合信号，并将数字化的组合信号提供给控制器。 控制器分离数字化调制载波信号和数字化音频信号。 数字化调制载波信号被解调以产生提供电子设备消耗的功率的量度的输出信号。

公开(公告)号：US20100158108A1

公开(公告)日：2010-06-24

申请号：US12636321

申请日：2009-12-11

Applicant: Megha AGARWAL ,  Sumit JOHAR ,  Kaushik SAHA ,  Emiliano Mario Piccinelli

Inventor： Megha AGARWAL ,  Sumit JOHAR ,  Kaushik SAHA ,  Emiliano Mario Piccinelli

IPC: H04N7/26

CPC classification number: H04N19/48 ,  H04N19/115 ,  H04N19/149 ,  H04N19/152 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61

Abstract: An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

Abstract translation: 本公开的实施例涉及一种包括编码装置的系统。 所述编码装置包括压缩单元，量化器，比特估计器，比特率编码器和可变长度编码器。 实施例也是一种编码方法。 所述方法估计在压缩数据流之后编码宏块的位数。 然后估计比特由比特率编码器编码并由量化器进一步量化以获得最终的编码比特流。 在量化处理之后和编码处理之前估计编码宏块所需的位数。 宏块比特估计器根据该宏块的量化AC系数和在宏块级标准化的相邻帧的量化AC系数来估计对特定宏块进行编码所需的比特数。