-
公开(公告)号：US20140082322A1
公开(公告)日：2014-03-20
申请号：US13617673
申请日：2012-09-14
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译： 存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。 存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。 物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。 存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。 物理地址映射可以针对整个存储器或基于每存储器区域编程。
-
公开(公告)号：US07725887B2
公开(公告)日：2010-05-25
申请号：US11020340
申请日：2004-12-22
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： In a method for reducing code size, replaceable subsets of instructions at first locations in areas of infrequently executed instructions in a set of instructions and target subsets of instructions at second locations in the set of instructions are identified, wherein each replaceable subset matches at least one target subset. If multiple target subsets of instructions match one replaceable subset of instructions, one of the multiple matching target subsets is chosen as the matching target subset for the one replaceable subset based on whether the multiple target subsets are located in regions of frequently executed code. For each of at least some of the replaceable subsets of instructions, the replaceable subset of instructions is replaced with an instruction to cause the matching target subset of instructions at the second location to be executed.
摘要翻译： 在减少代码大小的方法中，识别在一组指令中的不经常执行的指令的区域中的第一位置处的指令的可替换子集，以及指令集中的第二位置处的目标指令子集，其中每个可替换子集与至少一个 目标子集。 如果指令的多个目标子集匹配一个可替换的指令子集，则基于多个目标子集是否位于经常执行的代码的区域中，将多个匹配目标子集中的一个选择为一个可替换子集的匹配目标子集。 对于至少一些可替换的指令子集中的每一个，可替换的指令子集被替换为使得执行第二位置处的指令的匹配目标子集的指令。
-
公开(公告)号：US07694281B2
公开(公告)日：2010-04-06
申请号：US11241527
申请日：2005-09-30
申请人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
发明人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.
摘要翻译： 确定程序的第一个潜在的热迹。 确定程序的第二个潜在的热迹。 选择第一个潜在热痕迹和第二个潜在热痕迹的常见路径作为程序的选定热痕迹。
-
4.发明授权Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators 失效在两相动态二进制转换器中循环优化的连续行程计数分析公开(公告)号：US07428731B2
公开(公告)日：2008-09-23
申请号：US10816248
申请日：2004-03-31
CPC分类号： G06F9/45525
摘要： A method, machine readable medium, and system are disclosed. In one embodiment the method comprises collecting a loop trip count continuously during runtime of a region of code being executed that contains a loop, categorizing the trip count to identify one or more code modification techniques applicable to the loop, and dynamically applying the one or more applicable code modification techniques to alter the code that relates to the loop.
摘要翻译： 公开了一种方法，机器可读介质和系统。 在一个实施例中，该方法包括在包含循环的正在执行的代码区域的运行时期期间连续地收集循环行程计数，对行程计数进行分类，以识别适用于循环的一个或多个代码修改技术，以及动态地应用一个或多个 适用的代码修改技术来改变与循环相关的代码。
-
公开(公告)号：US06823070B1
公开(公告)日：2004-11-23
申请号：US09536520
申请日：2000-03-28
IPC分类号： H04K100
CPC分类号： H04L9/0894 , H04L2209/04
摘要： Method of monitoring a secure encrypted communication, where the encryption key(s) is recovered by an escrow center having a master and multiple agents and the master receives the key encrypted using a mask scheme. Independent random masks are generated, which are then used to create dependent masks for each agent. The agents receive the mask information but no key information. The agents decide whether to allow the interception of an encrypted message. In response to the agents' decisions, the master is either enabled to recover the key or prevented from recovering the key. Encrypted key information is only available to the master. Multiple combinations of agents will provide sufficient information to the master to recover the key, avoiding the hold-out problems of the prior art. In one embodiment, multiple masters provide back-up protection when a master is unavailable.
摘要翻译： 监控安全加密通信的方法，其中由具有主代理和多个代理的托管中心恢复加密密钥，并且主机接收使用掩码方案加密的密钥。 生成独立随机掩码，然后用它们为每个代理创建依赖掩码。 代理接收掩码信息，但没有密钥信息。 代理人决定是否允许拦截加密的消息。 响应于代理人的决定，主机可以启用恢复密钥或阻止恢复密钥。 加密的密钥信息仅适用于主服务器。 代理商的多个组合将向主机提供足够的信息以恢复密钥，避免现有技术的保留问题。 在一个实施例中，当主机不可用时，多个主机提供备用保护。
-
公开(公告)号：US5966143A
公开(公告)日：1999-10-12
申请号：US949356
申请日：1997-10-14
IPC分类号： G06F9/45
摘要： Data is allocated into multiple memories with selective variable replication for maximizing performance by minimizing concurrent memory access conflicts. Requirements for concurrent access are summarized in a transformed concurrent access graph. Graph vertices are merged to disallow variable replication. All potential graph merges that cause a reduction in machine cycle time are identified. The ratios of saved cycles/memory cost in bytes are then computed for each potential merge. The potential merges are then sorted by their saved cycles/bytes ratio. Finally, potential merges resulting in replicated variables are selected based on their cycles/bytes ratios until a predefined memory target size is achieved. Either graph coloring or clique partitioning can be used to allocate variables into memory banks.
摘要翻译： 数据被分配到具有选择性变量复制的多个存储器中，以通过最小化并发存储器访问冲突来最大化性能。 并发访问的要求在转换的并发访问图中汇总。 图形顶点被合并以禁止变量复制。 确定导致机器周期时间缩短的所有潜在图形合并。 然后为每个潜在的合并计算保存的周期/存储器成本（以字节为单位）的比率。 然后，潜在的合并按照保存的周期/字节比进行排序。 最后，基于它们的周期/字节比率来选择导致复制变量的潜在合并，直到达到预定义的存储器目标大小。 图形着色或集团划分可用于将变量分配到存储体中。
-
公开(公告)号：US09146846B2
公开(公告)日：2015-09-29
申请号：US13617673
申请日：2012-09-14
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译： 存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。 存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。 物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。 存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。 物理地址映射可以针对整个存储器或基于每存储器区域编程。
-
公开(公告)号：US20110320775A1
公开(公告)日：2011-12-29
申请号：US12824187
申请日：2010-06-27
申请人： Edson Borin , Mauricio Breternitz, JR. , Nir Bone , Shlomo Avni
发明人： Edson Borin , Mauricio Breternitz, JR. , Nir Bone , Shlomo Avni
CPC分类号： H03M7/30 , G06F9/30145 , G06F9/30178 , G06F9/382 , G06F9/445 , Y02D10/43
摘要： Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.
摘要翻译： 描述与加速压缩代码执行有关的方法和装置。 在一个实施例中，利用消除气泡的两级嵌入式代码解压缩方案，这可以增加速度和/或降低功耗。 还描述和要求保护其他实施例。
-
9.发明授权Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常公开(公告)号：US07757221B2
公开(公告)日：2010-07-13
申请号：US11241610
申请日：2005-09-30
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/443
摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
摘要翻译： 一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。 在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。 在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。 在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。 在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。 描述和要求保护其他实施例。
-
公开(公告)号：US20090172713A1
公开(公告)日：2009-07-02
申请号：US11968055
申请日：2007-12-31
CPC分类号： G06F9/30145 , G06F9/4552
摘要： Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.
摘要翻译： 方法和设备通过用户级异常处理实现按需指令仿真。 不支持的指令在程序运行时触发异常。 响应于异常，启动用户级或应用程序级异常处理程序，而不是内核级处理程序。 然后异常处理程序可以在应用程序层而不是内核级别执行。 处理程序标识指令并模拟指令，其中指令的仿真由处理程序支持。 仿真指令使程序能够继续执行。 重复的指令仿真通过热代码的动态二进制转换进行分摊。
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.023 秒)
