发明授权
US07757221B2 Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints
有权
用于动态二进制转换器的装置和方法,以最小的优化约束来支持精确异常
- 专利标题: Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints
- 专利标题(中): 用于动态二进制转换器的装置和方法,以最小的优化约束来支持精确异常
-
申请号: US11241610申请日: 2005-09-30
-
公开(公告)号: US07757221B2公开(公告)日: 2010-07-13
- 发明人: Bixia Zheng , Cheng C. Wang , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
- 申请人: Bixia Zheng , Cheng C. Wang , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F9/45
- IPC分类号: G06F9/45
摘要:
A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
公开/授权文献
信息查询