公开(公告)号：US20060062071A1

公开(公告)日：2006-03-23

申请号：US11198334

申请日：2005-08-08

申请人： Masaya Uehara ,  Eitaro Otsuka

发明人： Masaya Uehara ,  Eitaro Otsuka

IPC分类号： G11C8/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/12 ,  G11C2207/107

摘要： A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits, which is different from the latch circuit to which the data are formerly latched, included in the group of latch circuits corresponding to the same read amplifier; and the latched data are lastly outputted in a desired order from each of the latch circuits having the latched data.

摘要翻译： 半导体存储器件包括：以矩阵排列的多个存储单元; 被分成多个块的存储单元阵列; 多个读取放大器，每个读取放大器相应地耦合到每个块; 以及多个锁存电路，每组锁存电路相应地耦合到每个读取放大器并且包括并联耦合到彼此的两个或更多个锁存电路，其中为了从存储器单元阵列连续地读取多个数据 首先从每个块的一个期望的存储单元读取数据; 将读取数据通过对应于同一块的读取放大器第二次输入和锁存到与同一读取放大器对应的一组锁存电路中的锁存电路之一; 对于每个块，数据从与之前读取的数据的存储器单元不同的另一所需存储单元第三次读取; 读取数据经由对应于同一块的读取放大器被输入并锁存到与数据先前锁存的锁存电路不同的锁存电路之一中，锁存电路包括在对应于 相同的读取放大器; 并且锁存的数据最后以具有锁存数据的每个锁存电路的期望顺序输出。

公开(公告)号：US07085974B2

公开(公告)日：2006-08-01

申请号：US10314433

申请日：2002-12-06

申请人： Koji Miyashita ,  Masaya Uehara

发明人： Koji Miyashita ,  Masaya Uehara

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/12015 ,  G11C29/006 ,  G11C29/12

摘要： A semiconductor device having a plurality of memory cells for storing data, an address input circuit having an address signal generation section for independently generating an address signal using a clock signal in a test mode, and a delay circuit for delaying an input time of the address signal from the address input circuit to a subsequent circuit for a predetermined time period which is equal to or longer than the time necessary for the generation of the address signal.

公开(公告)号：US07212464B2

公开(公告)日：2007-05-01

申请号：US11198334

申请日：2005-08-08

申请人： Masaya Uehara ,  Eitaro Otsuka

发明人： Masaya Uehara ,  Eitaro Otsuka

IPC分类号： G11C8/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/12 ,  G11C2207/107

摘要： A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits, which is different from the latch circuit to which the data are formerly latched, included in the group of latch circuits corresponding to the same read amplifier; and the latched data are lastly outputted in a desired order from each of the latch circuits having the latched data.

摘要翻译： 半导体存储器件包括：以矩阵排列的多个存储单元; 被分成多个块的存储单元阵列; 多个读取放大器，每个读取放大器相应地耦合到每个块; 以及多个锁存电路，每组锁存电路相应地耦合到每个读取放大器并且包括并联耦合到彼此的两个或更多个锁存电路，其中为了从存储器单元阵列连续地读取多个数据 首先从每个块的一个期望的存储单元读取数据; 将读取数据通过对应于同一块的读取放大器第二次输入和锁存到与同一读取放大器对应的一组锁存电路中的锁存电路之一; 对于每个块，数据从与之前读取的数据的存储器单元不同的另一所需存储单元第三次读取; 读取数据经由对应于同一块的读取放大器被输入并锁存到与数据先前锁存的锁存电路不同的锁存电路之一中，锁存电路包括在对应于 相同的读取放大器; 并且锁存的数据最后以具有锁存数据的每个锁存电路的期望顺序输出。

公开(公告)号：US06594186B2

公开(公告)日：2003-07-15

申请号：US10171421

申请日：2002-06-12

申请人： Satoru Kodaira ,  Masaya Uehara ,  Hitoshi Kobayashi ,  Takeshi Kumagai

发明人： Satoru Kodaira ,  Masaya Uehara ,  Hitoshi Kobayashi ,  Takeshi Kumagai

IPC分类号： G11C2900

CPC分类号： G11C29/48 ,  G11C29/20

摘要： A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signal. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.

公开(公告)号：US20060056263A1

公开(公告)日：2006-03-16

申请号：US11201167

申请日：2005-08-11

申请人： Eitaro Otsuka ,  Masaya Uehara ,  Shuhei Nakayama

发明人： Eitaro Otsuka ,  Masaya Uehara ,  Shuhei Nakayama

IPC分类号： G11C8/00

CPC分类号： G11C8/04 ,  G11C7/1018 ,  G11C11/4076

摘要： A semiconductor memory device includes a plurality of banks including memory cell arrays in which dynamic type memory cells are arranged in a matrix, according to an input address and an input control command in synchronization with a clock signal, the memory cell corresponding to the input address being accessed in response to the input control command; wherein the input address is set as an X address for selecting a word line in the memory cell array, a Y address for selecting a data line pair in the memory cell array, and a bank address for selecting a bank, the bank address being placed in lower bits than the X address; and wherein, in burst operations that correspond to a sequence of addresses containing the input address as a leading address and consecutively perform access corresponding to the input control command to a plurality of memory cells arranged over the plurality of banks, in order for a sequence of memory cells included in one bank among the plurality of memory cells to be accessed, a word line corresponding to the sequence of memory cells is activated while a word line corresponding to a sequence of memory cells included in another bank to be accessed subsequent to access to the sequence of memory cells included in the one bank is activated in advance, and access to the sequence of memory cells included in the one bank and access to the sequence of memory cells included in the another bank are consecutively performed in synchronization with the clock signal.

摘要翻译： 半导体存储器件包括多个存储体，包括存储单元阵列，其中根据与时钟信号同步的输入地址和输入控制命令，以矩阵形式布置动态类型存储单元，存储单元对应于输入地址 响应于输入控制命令被访问; 其中输入地址被设置为用于选择存储单元阵列中的字线的X地址，用于选择存储单元阵列中的数据线对的Y地址和用于选择存储体的存储体地址，所述存储体地址被放置 在比X地址低的位; 并且其中，在对应于包含所述输入地址的地址序列作为前导地址的突发操作中，并且对与所述多个存储体上布置的多个存储器单元连续执行对应于所述输入控制命令的访问，以便顺序地 在要访问的多个存储器单元中包含一个存储单元的存储单元被激活，对应于存储单元序列的字线被激活，而对应于包含在另一个存储体中的存储器单元序列的字线将被访问 预先激活包括在一个存储体中的存储单元的序列，并且与时钟信号同步地连续地执行对包括在一个存储体中的存储单元序列的访问以及对包括在另一个存储体中的存储单元序列的访问 。

公开(公告)号：US06868304B2

公开(公告)日：2005-03-15

申请号：US10670197

申请日：2003-09-26

申请人： Masaya Uehara ,  Miwako Yuhara

发明人： Masaya Uehara ,  Miwako Yuhara

IPC分类号： B23Q11/08 ,  B23B3/16 ,  B23B5/46 ,  B23B5/48 ,  B23B21/00 ,  B23C3/32 ,  B23F13/06 ,  B23F15/08 ,  B23P23/02 ,  B23Q1/62 ,  G06F19/00

CPC分类号： B23Q1/623 ,  B23B5/48 ,  B23F15/08 ,  Y10T82/2543 ,  Y10T483/1771

摘要： The multi-function machine tool of the present invention has a tool rest main body which is disposed movably relative to the main spindle of the machine tool in a first linear direction parallel to the axial line of the main spindle and a second linear direction perpendicular to the axial line of the main spindle, a turning tool rest 72 which is disposed so that this turning tool rest can turn relative to the tool rest main body about a turning axis 73 oriented in a direction that is perpendicular to the first and second linear directions, and control means which control the rotational motion of the main spindle, the turning motion of the turning tool rest about the turning axis, and the relative motion of the tool rest main body. Furthermore, the control means can cause the turning tool rest to perform a turning motion about an arbitrary position that differs from the position of the turning axis by concurrently and synchronously causing a turning motion of the turning tool rest about the turning axis, and a circular-arc motion based on the relative motion of the tool rest main body in the first linear direction and second linear direction.

摘要翻译： 本发明的多功能机床具有：刀具主体，其相对于机床的主轴在与主轴的轴线平行的第一直线方向上相对移动地设置，第二直线方向垂直于 主轴的轴线，转动刀架72，其设置成使得该转动刀架能够相对于刀架主体绕相对于第一和第二直线方向定向的转动轴线73转动 以及控制装置，其控制主轴的旋转运动，转动工具围绕转动轴线的转动运动以及刀架主体的相对运动。 此外，控制装置可以使转动刀架在与转动轴的位置不同的任意位置上同时并且同时引起转动刀架围绕转动轴线的转动运动而进行转动运动，圆周 基于刀架主体在第一线性方向和第二线性方向上的相对运动的运动。