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公开(公告)号：US11748418B2
公开(公告)日：2023-09-05
申请号：US16264248
申请日：2019-01-31
IPC分类号： G06F12/1045 , G06F15/173 , H04L49/901 , H04L67/1097 , G06F16/907 , G06F16/901 , G06F16/9038 , G06F16/9035 , G06F16/783 , G06F16/387 , G06F16/683 , G06F16/383 , G06F3/06 , G06N3/08
CPC分类号： G06F16/907 , G06F3/0604 , G06F3/068 , G06F3/0638 , G06F3/0659 , G06F3/0688 , G06F12/1054 , G06F15/17331 , G06F16/383 , G06F16/387 , G06F16/683 , G06F16/783 , G06F16/901 , G06F16/9035 , G06F16/9038 , G06N3/08 , H04L49/901 , H04L67/1097 , G06F2212/254
摘要： This disclosure describes a storage aggregator controller with metadata computation control. The storage aggregator controller communicates, via a host interface, over a computer network with one or more remote hosts, and also communicates, via a storage device interface, with a plurality of local storage devices, which are separate from the remote host(s) and which have respective non-volatile memories. The storage aggregator controller manages the local storage devices for storage or retrieval of media objects. The storage aggregator controller also governs a selective computation, at aggregator control circuitry or at a storage device controller of one or more of the storage devices, of metadata that defines content characteristics of the media objects that are retrieved from the plurality of storage devices or that are received from the one or more hosts over the computer network for storage in the plurality of storage devices.
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公开(公告)号：US11258555B1
公开(公告)日：2022-02-22
申请号：US16663929
申请日：2019-10-25
发明人： Tong Ji , Yen-Kai Chen , Sai Man Simon Wong , Mao Yu
IPC分类号： H04L5/00
摘要： Embodiments described herein provide systems for processing high efficiency SIGB (HE-SIGB) symbols and extracting resource unit (RU) information in down link orthogonal frequency division multiple access (DL-OFDMA) and multi-user multiple input multiple output (DL-MUMIMO) communication. An HE-SIGB symbol is processed based on an RU size mapping table. An RU counter is used to process entries in the RU size mapping table and determine the RU size and starting tone index of the intended RU. The RU parameters extracted from the HE-SIGB symbol are used to decode data symbols in the DL-OFDMA or DL-MUMIMO packet. Pilot tone indices of the intended User block and adjacent pilot tone indices are determined for improved carrier phase error estimation.
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公开(公告)号：US11250135B1
公开(公告)日：2022-02-15
申请号：US16527302
申请日：2019-07-31
摘要： A programmable integrated circuit device includes a programmable core, a boot device configured to boot up the programmable core, and a one-time programmable memory module controlling life cycle states of the programmable integrated circuit device, including (i) an operational state during which programming resources of the programmable device are locked, and (ii) an inspection state in which the programming resources of the programmable device are accessible. The one-time programmable memory module is configured to allow unidirectional advance from the operational state to the inspection state, when authorized by a lock control circuit responsive to control signals from the boot device to authorize the unidirectional advance from the operational state to the inspection state. Authorization of the unidirectional advance may be limited to a time interval during a boot cycle of the programmable device. The unidirectional advance may be based on receipt of an authenticated request from a requester.
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公开(公告)号：US11223439B1
公开(公告)日：2022-01-11
申请号：US16682713
申请日：2019-11-13
摘要： A physical layer circuit includes registers and a timing circuit. The registers are configured to store a future time of day, a local hardware time and a compensation value. The timing circuit is configured to: determine a relationship between the local hardware time and a grandmaster time; select the future time of day; determine a difference between a local clock and a grandmaster clock and set the compensation value equal to the difference; subsequent to determining the difference, enable maintenance of a current time of day; when the local hardware time matches the future time of day, begin updating the current time of day based on the compensation value to match the grandmaster time; and adjust the compensation value to compensate for drift between the current time of day and the grandmaster time.
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公开(公告)号：US11176055B1
公开(公告)日：2021-11-16
申请号：US16532654
申请日：2019-08-06
IPC分类号： G06F12/1009 , G06F12/1045 , G06F9/30 , G06F9/38
摘要： A pipeline in a processor core includes: at least one stage that decodes instructions including load instructions that retrieve data stored at respective virtual addresses, at least one stage that issues at least some decoded load instructions out-of-order, and at least one stage that initiates at least one prefetch operation. Copies of page table entries mapping virtual addresses to physical addresses are stored in a TLB. Managing misses in the TLB includes: handling a load instruction issued out-of-order using a hardware page table walker, after a miss in the TLB, handling a prefetch operation using the hardware page table walker, after a miss in the TLB, and handling any software-calling faults triggered by out-of-order load instructions handled by the hardware page table walker differently from any software-calling faults triggered by prefetch operations handled by the hardware page table walker.
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6.发明授权公开(公告)号：US11166159B1
公开(公告)日：2021-11-02
申请号：US16005437
申请日：2018-06-11
摘要： The present disclosure describes methods and apparatuses for secure fine timing measurement (FTM) with encoded long training fields (LTFs). In some aspects, a device transmits an announcement frame for an FTM exchange that includes an indication of encoding. Based on the indication of encoding, an LTF of a first null data packet (NDP) of the FTM exchange is encoded. The device transmits the first NDP having the encoded LTF to another device, and receives, from the other device, a second NDP having an encoded LTF. A round-trip time for the first and second NDPs with encoded LTFs is determined. Based on this round-trip time, a distance between the device and the other device can be determined. By encoding the LTFs of the NDPs of the FTM exchange, third parties can be prevented from spoofing an FTM frame to compromise the FTM exchange and related proximity-based security.
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公开(公告)号：US11129091B2
公开(公告)日：2021-09-21
申请号：US16421917
申请日：2019-05-24
发明人： Sabih Guzelgoz , Hong Jik Kim
摘要： Methods and apparatus for providing a resource element identification system to process received uplink transmissions. In an embodiment, a method is provided that includes receiving one or more symbols from an uplink transmission. Each symbol comprises resource elements. The method also includes categorizing the resource elements into a plurality of categories to generated categorized resource elements, and forwarding the categorized resource elements to downstream processing functions.
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公开(公告)号：US11119530B1
公开(公告)日：2021-09-14
申请号：US16176815
申请日：2018-10-31
发明人： Alex Pinskiy , Eyal Herzog
摘要： Aspects of the disclosure provide an electronic device. The electronic device can include a first clock gating circuit that is configured to receive a clock signal and selectively transmit a clock pulse of the clock signal when triggered, access circuitry configured to launch configuration data in response to receiving a write request from a management module and trigger the first clock gating circuit to generate a first clock pulse that is delayed by a first predetermined amount of time after the launch of the configuration data by the access circuitry, and a first memory element configured to capture the configuration data in response to receiving the delayed first clock pulse generated by the first clock gating circuit.
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公开(公告)号：US20210223809A1
公开(公告)日：2021-07-22
申请号：US16748674
申请日：2020-01-21
摘要： Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system. The system includes multiple parameter generators (e.g., voltage generators, current generators, capacitance generators, etc.) and an integrated calibration circuit. The calibration circuit is configured to automatically, sequentially, and repeatedly calibrate the parameter generators in order to minimize chip-to-chip variations in parameters supplied to other on-chip components under real world operating conditions throughout the life of the IC chip. In other words, the integrated calibration circuit effectively minimizes temperature-induced chip-to-chip variations, age-induced chip-to-chip variations, etc. in parameters generated by the on-chip parameter generators. Also disclosed herein are embodiments of an associated method.
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10.发明申请公开(公告)号：US20210192336A1
公开(公告)日：2021-06-24
申请号：US16724554
申请日：2019-12-23
摘要： Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.
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