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1.发明申请公开(公告)号：US20210192336A1
公开(公告)日：2021-06-24
申请号：US16724554
申请日：2019-12-23
Applicant: Marvell International Ltd.
Abstract: Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.
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公开(公告)号：US11580059B2
公开(公告)日：2023-02-14
申请号：US16527100
申请日：2019-07-31
Applicant: MARVELL INTERNATIONAL LTD.
Inventor： Venkatraghavan Bringivijayaraghavan , Aravindan J. Busi , Deepak I. Hanagandi , Igor Arsovski
IPC: G06F15/80 , G06F3/06 , G11C11/419
Abstract: A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.
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公开(公告)号：US20210034567A1
公开(公告)日：2021-02-04
申请号：US16527100
申请日：2019-07-31
Applicant: MARVELL INTERNATIONAL LTD.
Inventor： Venkatraghavan Bringivijayaraghavan , Aravindan J. Busi , Deepak I. Hanagandi , Igor Arsovski
IPC: G06F15/80 , G06F3/06 , G11C11/419
Abstract: A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.
