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公开(公告)号：US11223439B1
公开(公告)日：2022-01-11
申请号：US16682713
申请日：2019-11-13
摘要： A physical layer circuit includes registers and a timing circuit. The registers are configured to store a future time of day, a local hardware time and a compensation value. The timing circuit is configured to: determine a relationship between the local hardware time and a grandmaster time; select the future time of day; determine a difference between a local clock and a grandmaster clock and set the compensation value equal to the difference; subsequent to determining the difference, enable maintenance of a current time of day; when the local hardware time matches the future time of day, begin updating the current time of day based on the compensation value to match the grandmaster time; and adjust the compensation value to compensate for drift between the current time of day and the grandmaster time.
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公开(公告)号：US10862601B1
公开(公告)日：2020-12-08
申请号：US16416954
申请日：2019-05-20
IPC分类号： H04J3/06 , H04L12/803
摘要： A switching device is provided and includes a processor and a physical layer device. The processor is configured to generate a synchronization frame and a corresponding follow up frame. The follow up frame is generated while or subsequent to the generating of the synchronization frame and without waiting for an egress timestamp indicating when the synchronization frame is to be transmitted from the switching device to a network device. The physical layer device is configured to: receive the synchronization and follow up frames from the processor; prior to transmitting the follow up frame to the network device, modify the follow up frame to include the egress timestamp indicating when the synchronization frame is transmitted from the switching device via the physical layer device; and perform a precision time protocol process including transmitting the synchronization and follow up frames from the switching device to the network device for clock synchronization.
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公开(公告)号：US10298344B1
公开(公告)日：2019-05-21
申请号：US15060719
申请日：2016-03-04
IPC分类号： H04J3/06
摘要： A network device is provided and includes a physical layer module and a control port. The physical layer module includes one or more ports, which: receives and alters a first synchronization frame to include a timestamp indicating a received time. The control port: receives the first synchronization frame from the one or more ports; provides the first synchronization frame to a control module; and receives, from the control module a second synchronization frame including the timestamp and a follow up frame corresponding to the second synchronization frame. The one or more ports: receives the second synchronization and follow up frames from the control port and transmits the received frames from the network device; and generates an egress timestamp for the second synchronization frame and updates a timestamp field of the follow up frame or calculates a residence time and updates a correction field of the follow up frame.
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公开(公告)号：US10084559B1
公开(公告)日：2018-09-25
申请号：US15060732
申请日：2016-03-04
CPC分类号： H04J3/0661 , H04J3/0667 , H04J3/0673 , H04J3/0697 , H04L47/125
摘要： A network device including a port having register and timing modules. The register module includes first ToD, loadpoint, and compensation registers. The timing module includes a second ToD register and ToD module and operates based on a local clock signal. The register module receives a ToD from a control module, which is separate from the network device and selects an initial hardware time. The ToD is a future time and is based on a grandmaster clock signal. The first ToD and loadpoint registers store the ToD and initial hardware time. The compensation register stores a compensation value from the control module and determined based on a difference between local and grandmaster clock signals. The ToD module, when local and initial hardware times match: transfers the ToD between first and second ToD registers; and updates the ToD in the second ToD register based on the local clock signal and compensation value.
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