公开(公告)号：US20080080443A1

公开(公告)日：2008-04-03

申请号：US11529146

申请日：2006-09-28

申请人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

发明人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

IPC分类号： H04B7/216

CPC分类号： H04B1/7105 ,  H04B2201/70707

摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.

摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。

公开(公告)号：US07266160B2

公开(公告)日：2007-09-04

申请号：US10689330

申请日：2003-10-20

申请人： Marko Kocic ,  Lidwine Martinot ,  Zoran Zvonar

发明人： Marko Kocic ,  Lidwine Martinot ,  Zoran Zvonar

IPC分类号： H04L25/06

CPC分类号： H04L25/062 ,  H04L25/0216 ,  H04L25/023 ,  H04L25/025

摘要： Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.

摘要翻译： 虽然DC偏移降低方案可以应用在模拟域中，但基带中的残留静态DCO仍然存在，从而显着影响近来高数据速率无线通信标准采用的高级调制方案的性能。 为了达到令人满意的性能，数字领域需要DCO补偿算法。 开发了一种这样的算法，其基于通道脉冲响应（CIR）和静态DCO的联合估计，并且确保具有直接转换无线电架构的EDGE调制解调器的令人满意的性能。 联合估计算法（所谓的“扰动关节L”）的进一步修改导致EDGE均衡器在关键衰落信道中的性能的进一步改进。

公开(公告)号：US07953958B2

公开(公告)日：2011-05-31

申请号：US11818055

申请日：2007-06-12

申请人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

发明人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

IPC分类号： G06F15/76 ,  G06F9/302

CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04B2201/70711

摘要： A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

摘要翻译： 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

公开(公告)号：US20080080542A1

公开(公告)日：2008-04-03

申请号：US11529148

申请日：2006-09-28

申请人： Krishnan Vishwanathan ,  Deepak Mathew ,  Eric Aardoom ,  Lidwine Martinot ,  Aiguo Yan ,  Timothy Fisher-Jeffes ,  Paul D. Krivacek

发明人： Krishnan Vishwanathan ,  Deepak Mathew ,  Eric Aardoom ,  Lidwine Martinot ,  Aiguo Yan ,  Timothy Fisher-Jeffes ,  Paul D. Krivacek

IPC分类号： H04L12/56

CPC分类号： H04B1/707 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/0067

摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.

摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。

公开(公告)号：US20080080468A1

公开(公告)日：2008-04-03

申请号：US11818055

申请日：2007-06-12

申请人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

发明人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

IPC分类号： H04B7/216

CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04B2201/70711

摘要： A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

摘要翻译： 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

公开(公告)号：US08358988B2

公开(公告)日：2013-01-22

申请号：US11529146

申请日：2006-09-28

申请人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

发明人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

IPC分类号： H04B1/18

CPC分类号： H04B1/7105 ,  H04B2201/70707

摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级 并且提供编码的传输信道数据。 后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

公开(公告)号：US07916841B2

公开(公告)日：2011-03-29

申请号：US11545857

申请日：2006-10-11

申请人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  John Zijun Shen

发明人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  John Zijun Shen

IPC分类号： H04M1/64 ,  H04L25/49

CPC分类号： H04B1/7105 ,  H04B2201/70711

摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。

公开(公告)号：US20080089448A1

公开(公告)日：2008-04-17

申请号：US11546062

申请日：2006-10-11

申请人： Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic ,  Thomas J. Barber ,  John Zijun Shen

发明人： Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic ,  Thomas J. Barber ,  John Zijun Shen

IPC分类号： H04L27/06

CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04L25/0224

摘要： A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括联合检测器加速器，其被配置为执行对接收信号的联合检测的操作，其中联合检测包括计算关节检测变量。 该操作包括产生累加器中的值的乘法和累加运算，累加器中的值包括多个位。 联合检测器加速器被配置为选择累加器中的值的多个比特的子集，其中选择的比特的子集是可配置的。 联合检测器加速器还被配置为将位的子集存储到存储器中作为固定点表示。

公开(公告)号：US20050204208A1

公开(公告)日：2005-09-15

申请号：US10988142

申请日：2004-11-12

申请人： Marko Kocic ,  Lidwine Martinot ,  Zoran Zvonar

发明人： Marko Kocic ,  Lidwine Martinot ,  Zoran Zvonar

IPC分类号： G01R31/28 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04L27/38

CPC分类号： H04L25/0216 ,  H04L25/061

摘要： A receiver unit includes a prefilter that receives as one of the inputs a channel impulse response (CIR) estimation data set and removes unnecessary data information from the CIR estimation data set and filters input signal so to form a first output data set. An equalizer core receives the first output data set and based on computed CIR length and SNR value of the first output data set so as to determine which portion of the first output data set are assigned to at least one of at least two low complexity equalization modules used for processing.

摘要翻译： 接收机单元包括预滤波器，其接收作为输入的输入之一的信道脉冲响应（CIR）估计数据集，并从CIR估计数据集中去除不需要的数据信息，并对输入信号进行滤波，从而形成第一输出数据组。 均衡器核心接收第一输出数据集并且基于计算的第一输出数据集的CIR长度和SNR值，以便确定第一输出数据集的哪一部分被分配给至少两个低复杂度均衡模块中的至少一个 用于加工。

公开(公告)号：US20050084039A1

公开(公告)日：2005-04-21

申请号：US10689330

申请日：2003-10-20

申请人： Marko Kocic ,  Lidwine Martinot ,  Zoran Zvonar

发明人： Marko Kocic ,  Lidwine Martinot ,  Zoran Zvonar

IPC分类号： H04L25/02 ,  H04L25/06

CPC分类号： H04L25/062 ,  H04L25/0216 ,  H04L25/023 ,  H04L25/025

摘要： Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.

摘要翻译： 虽然DC偏移降低方案可以应用在模拟域中，但基带中的残留静态DCO仍然存在，从而显着影响近来高数据速率无线通信标准采用的高级调制方案的性能。 为了达到令人满意的性能，数字领域需要DCO补偿算法。 开发了一种这样的算法，其基于通道脉冲响应（CIR）和静态DCO的联合估计，并且确保具有直接转换无线电架构的EDGE调制解调器的令人满意的性能。 联合估计算法（所谓的“扰动关节L”）的进一步修改导致EDGE均衡器在关键衰落信道中的性能的进一步改进。