公开(公告)号：US6101196A

公开(公告)日：2000-08-08

申请号：US30421

申请日：1998-02-25

申请人： Kurenai Murakami

发明人： Kurenai Murakami

IPC分类号： H04L7/00 ,  H04J3/06 ,  H04L7/02 ,  H04L12/70 ,  H04L12/951 ,  H04Q3/00 ,  H04Q11/04 ,  H04L7/08

CPC分类号： H04J3/0632 ,  H04Q11/0478 ,  H04L2012/5654 ,  H04L2012/5674

摘要： An SRTS receiver for reproducing a user clock by applying combined pulses to phase synchronous oscillation unit, the SRTS receiver comprises a RTS information receiving unit for generating pulses in N-clock cycle of the user clock on average according to the received RTS information, an interpolation pulse generating unit for generating interpolation pulse signals to be inserted in the pulses generated by the RTS information receiving unit, and a pulse combining unit for combining the interpolation pulses supplied from the interpolation pulse generating unit and the pulses generated by the RTS information receiving unit and supplying the same.

摘要翻译： SRTS接收机，用于通过向相位同步振荡单元施加组合脉冲来再现用户时钟，SRTS接收机包括RTS信息接收单元，用于根据接收到的RTS信息平均产生用户时钟的N时钟周期的脉冲， 用于产生要插入由RTS信息接收单元产生的脉冲的插值脉冲信号的脉冲产生单元;以及脉冲组合单元，用于组合从内插脉冲发生单元提供的内插脉冲和由RTS信息接收单元产生的脉冲;以及 供应相同。

公开(公告)号：US07269225B2

公开(公告)日：2007-09-11

申请号：US10629596

申请日：2003-07-30

申请人： Takahiro Shiozawa ,  Kurenai Murakami ,  Nobuto Kawataka

发明人： Takahiro Shiozawa ,  Kurenai Murakami ,  Nobuto Kawataka

IPC分类号： H04K1/10

CPC分类号： H04N21/4305 ,  H04J3/0632 ,  H04N21/23602 ,  H04N21/242 ,  H04N21/4342

摘要： A serial digital signal transmission apparatus can transmit HDTV digital serial signals with little jitter while utilizing the SRTS method. In the apparatus, parallel clocks are counted by an N counter to be supplied to the latch circuit, which latches the output count of a p-bit counter, RTSs are supplied from the latch circuit, as the result of comparison gated by a gate circuit is supplied to a PLL circuit and multiplied by N, parallel clocks of 74.25 MHz or 74.25/1.001 MHz, which are inputs to the N counter are regenerated (N is 8, 15 or 16), and transmitted data undergo parallel-to-serial conversion by a PS converter with these parallel clocks.

摘要翻译： 串行数字信号传输装置可以在利用SRTS方法的情况下传输具有很小抖动的HDTV数字串行信号。 在该装置中，由N个计数器对并行时钟进行计数，以提供给锁存电路，该锁存电路锁存p位计数器的输出计数，作为由门电路门控的比较结果，从锁存电路提供RTS 被提供给PLL电路并乘以N，74.25MHz或74.25 / 1.001MHz的并行时钟，N个计数器的输入被再生（N为8,15或16），并且发送的数据经过并行到串行 由这些并行时钟的PS转换器进行转换。

公开(公告)号：US06658074B1

公开(公告)日：2003-12-02

申请号：US09577074

申请日：2000-05-23

申请人： Kurenai Murakami

发明人： Kurenai Murakami

IPC分类号： H04L700

CPC分类号： H03L7/197 ,  H04J3/076

摘要： In a clock signal reproducing circuit in a pulse stuffed synchronizing system, a destuffing circuit removes stuff pulses and unnecessary bits from a higher order group signal to output a lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. A storage circuit stores the lower order group signal outputted from the destuffing circuit. A stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. A variable frequency divider frequency-divides a clock signal of the higher order group signal based on the control signal outputted from the control circuit. A phase synchronization oscillation circuit reproduces a clock signal of the lower order group signal based on the frequency-divided clock signal outputted from the variable frequency divider.

摘要翻译： 在脉冲填充同步系统中的时钟信号再现电路中，去填充电路从高阶组信号中去除填充脉冲和不必要的位，以输出较低阶组信号，并输出表示存在或不存在正电荷的填充数据， 高阶组信号中的负值。 存储电路存储从去填充电路输出的低阶组信号。 填充率确定电路基于从去混合电路输出的填充数据，从正数填充数和负数的差到高阶组信号的填充可能周期来确定填充率。 可变分频器根据从控制电路输出的控制信号，对高阶组信号的时钟信号进行分频。 相位同步振荡电路基于从可变分频器输出的分频时钟信号再现低阶组信号的时钟信号。

公开(公告)号：US4920547A

公开(公告)日：1990-04-24

申请号：US127498

申请日：1987-12-01

申请人： Kurenai Murakami

发明人： Kurenai Murakami

IPC分类号： H04J3/07 ,  H04L7/00

CPC分类号： H04J3/073

摘要： A stuff synchronization circuit includes a memory, a phase comparison D flip-flop, a stuff judgment flip-flop, and a control section including selectors and an encoder. In the memory, writing and reading are performed at different timings. The phase comparison D flip-flop detects a phase difference between a write timing for a specific bit included in data input to the memory and a read timing for the specific bit. The stuff judgment D flip-flop judges an insertion timing of stuff pulses on the basis of the detected phase difference. The control section keeps a time interval between a time at which the phase difference is detected by the phase comparison D flip-flop and a time at which the insertion timing of stuff pulses is judged by the stuff judgment D flip-flop constant.

摘要翻译： 填充同步电路包括存储器，相位比较D触发器，填充判断触发器以及包括选择器和编码器的控制部分。 在内存中，写入和读取在不同的时间进行。 相位比较D触发器检测包括在输入到存储器的数据中的特定位的写入定时与特定位的读取定时之间的相位差。 填充判断D触发器基于检测到的相位差来判定填充脉冲的插入定时。 控制部分保持由相位比较D触发器检测相位差的时间与由填充判定D触发器常数判断填充脉冲的插入定时的时间间隔。

公开(公告)号：US07126950B2

公开(公告)日：2006-10-24

申请号：US09782879

申请日：2001-02-13

申请人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

发明人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

IPC分类号： H04L12/28 ,  H03M13/00

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L1/0079 ,  H04L1/0085

摘要： A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

摘要翻译： 存储电路定义用于存储第一数据单元的第一有效载荷信号的第一标题位的第一字段，用于存储第一有效载荷信号的第二字段和第三字段。 第一标题位在第二数据单元的第二有效载荷信号的数量与第二标题位相等。 分割电路将第一标题位除以生成多项式以产生第一错误校验码。 使用相同的生成多项式来分割第二标题位以产生第二错误校验码。 通过生成多项式将假设标题位的余数除以第一错误校验码，以产生插入存储电路的第二字段的和。 假设的头部位数量大于第一和第二场域中总位数，从而第一和第二数据单元可以通过第一和第二数据单元的不同错误检查结果彼此区分开。

公开(公告)号：US06330242B1

公开(公告)日：2001-12-11

申请号：US09114135

申请日：1998-07-13

申请人： Makoto Ogawa ,  Motoo Nishihara ,  Michio Masuda ,  Kurenai Murakami

发明人： Makoto Ogawa ,  Motoo Nishihara ,  Michio Masuda ,  Kurenai Murakami

IPC分类号： H04L1228

CPC分类号： H04L45/10 ,  H04L45/34 ,  H04L69/16 ,  H04L69/161 ,  H04L69/168 ,  H04L2012/562 ,  H04L2012/5652 ,  H04L2012/5667 ,  H04Q11/0478

摘要： A loose source routing method is provided to transfer an IP packet from a transmission source gateway to a transfer destination gateway by way of ATM nodes, which are freely designated. At the transmission source gateway, the IP packet given from a user LAN is dissolved into ATM cells containing a BOM cell whose destination address designates the transfer destination gateway. In addition, at least one pseudo BOM cell whose destination address designates an ATM node in the ATM network is added and is located at a top place of a cell stream constructed by the dissolved ATM cells. Thus, the cell stream is transferred from the transmission source gateway to the designated ATM node in accordance with the destination address of the pseudo BOM cell. The designated ATM node discards the pseudo BOM cell so that the original BOM cell is now located at the top place of the cell stream. Then, the cell stream is transferred from the ATM node to the transfer destination gateway in accordance with the destination address of the BOM cell. The transfer destination gateway assembles the ATM cells into the IP packet, which is then sent to a user LAN.

摘要翻译： 提供了一种松散的源路由方法，用于通过自动指定的ATM节点将IP分组从传输源网关传送到传输目的地网关。 在传输源网关，从用户LAN给出的IP分组被解析成包含目的地地址指定传输目的网关的BOM小区的ATM信元。 此外，至少一个其目的地地址指定ATM网络中的ATM节点的伪BOM小区被添加并且位于由解决的ATM信元构成的小区流的顶部。 因此，根据伪BOM小区的目的地地址，将小区流从传输源网关传送到指定的ATM节点。 指定的ATM节点丢弃伪BOM单元，使得原始BOM单元现在位于单元流的顶部。 然后，根据BOM小区的目的地地址，将该小区流从ATM节点传送到传送目的地网关。 传输目的地网关将ATM信元组装成IP包，然后发送给用户LAN。

公开(公告)号：US5850401A

公开(公告)日：1998-12-15

申请号：US646381

申请日：1996-05-31

申请人： Kurenai Murakami

发明人： Kurenai Murakami

IPC分类号： H03M7/16 ,  H04J3/06 ,  H04L12/70 ,  H04L12/951 ,  H04Q11/04

CPC分类号： H04J3/0632 ,  H04Q11/0478 ,  H04L2012/5649 ,  H04L2012/5674

摘要： In an RTS generator used in an ATM network where a network reference clock is continuously counted to produce the lower four bits of a counted number, which are, in turn, latched in response to a latching pulse signal produced by frequency dividing a CBR clock by N=3008, the latched number providing the RTS, the lower four bits are formed on the base of the Gray code so as to avoid latching of abnormal number even in racing condition between the change of the counted number and a rising of the latching pulse.

摘要翻译： 在ATM网络中使用的RTS发生器中，其中网络参考时钟被连续计数以产生计数的较低的四位，其又响应于通过将CBR时钟分频产生的锁存脉冲信号而被锁存 N = 3008，提供RTS的锁存号码，下面的四位形成在格雷码的基础上，以便即使在计数数字的改变和锁存脉冲的上升之间的竞争条件下也可以避免锁定异常数 。

公开(公告)号：US20060193325A1

公开(公告)日：2006-08-31

申请号：US11414415

申请日：2006-05-01

申请人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

发明人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

IPC分类号： H04L12/28

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L1/0079 ,  H04L1/0085

摘要： A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

公开(公告)号：US5905411A

公开(公告)日：1999-05-18

申请号：US931202

申请日：1997-09-16

申请人： Kurenai Murakami ,  Kaoru Yoshida

发明人： Kurenai Murakami ,  Kaoru Yoshida

IPC分类号： H04L7/033 ,  H03L7/099 ,  H03L7/06

CPC分类号： H03L7/0991

摘要： A numerically controlled oscillator including an RTS value producing circuit which produces a series of residual time stamp (RTS) values indicative of a relation between the setting value and an actual oscillation frequency. A pulse train generator generates a pulse train in a period corresponding to the produced series of RTS values and a phase synchronous oscillator oscillates at a frequency in synchronism with the pulse train output from the pulse train generator. Preferably, the pulse train generated by the pulse train generator is supplied to the RTS value producing circuit as a signal indicative of the actual oscillation frequency.

摘要翻译： 一种数控振荡器，包括RTS值产生电路，产生一系列指示设定值与实际振荡频率之间关系的残余时间戳（RTS）值。 脉冲串发生器在对应于所产生的一系列RTS值的周期内产生脉冲序列，并且相位同步振荡器以与从脉冲串发生器输出的脉冲串同步的频率振荡。 优选地，由脉冲串发生器产生的脉冲序列作为表示实际振荡频率的信号提供给RTS值产生电路。

公开(公告)号：US5113395A

公开(公告)日：1992-05-12

申请号：US582567

申请日：1990-09-14

申请人： Kurenai Murakami ,  Tutomu Murase

发明人： Kurenai Murakami ,  Tutomu Murase

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04L7/00 ,  H04L7/08

CPC分类号： H04J3/0623

摘要： In a frame aligner for frame aligning an input time-division multiplexed (TDM) signal to an output frame synchronous signal, an input frame signal of the TDM signal is separated into a transport overhead carrying an input frame synchronous signal and a message pointer and a subframe carrying data signal. A fresh overhead having a fresh pointer is made corresponding to a phase difference between said input and said output frame synchronous signals and said subframe is sequentially written into and read from a buffer memory. The fresh overhead and the subframe read are multiplexed to form an output TDM frame signal which is synchronized with the output frame synchronous signal. The buffer memory is permitted to have a reduced memory capacity storable a number of channel signals equal to that of time slots carrying the overhead. When the input frame signal is asynchronous with an output clock signal, the input frame signal is converted to a converted frame signal which is synchronized with the output clock signal before the frame alignment is performed.

摘要翻译： 在用于将输入时分复用（TDM）信号与输出帧同步信号进行帧对准的帧对准器中，TDM信号的输入帧信号被分成携带输入帧同步信号和消息指针的传输开销， 子帧承载数据信号。 对应于所述输入和所述输出帧同步信号之间的相位差，产生具有新鲜指针的新开销，并且所述子帧被顺序地写入缓冲存储器并从缓冲存储器读取。 新开销和子帧读取被复用以形成与输出帧同步信号同步的输出TDM帧信号。 缓冲存储器被允许具有可存储多个信道信号的减少的存储容量等于承载开销的时隙的信道信号。 当输入帧信号与输出时钟信号异步时，输入帧信号被转换成在执行帧对准之前与输出时钟信号同步的转换帧信号。