公开(公告)号：US20070130242A1

公开(公告)日：2007-06-07

申请号：US11385718

申请日：2006-03-22

申请人： Kunihiko Tajiri

发明人： Kunihiko Tajiri

IPC分类号： G06F7/00

CPC分类号： G06F5/012 ,  G06F7/483 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/5443 ,  G06F7/74 ,  G06F2207/382

摘要： An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit outputting the arithmetic operation result, a normalizer having a plurality of shifter normalizing the arithmetic operation result, a shift amount calculator calculating a plurality of shift amounts for the plural shifter, and a predictor generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator generating the information by using the interim information. The cycle time required to generate a sticky bit is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit is reduced.

摘要翻译： 算术运算部，生成表示算术运算结果归一化时算术运算结果是否移位的信息，具有输出算术运算结果的算术运算部，具有使运算结果归一化的多个移位器的归一化部 ，计算多个移位器的多个移位量的移位量计算器，以及作为在算术运算结果被归一化时算术运算结果是否移位的预测结果的预测器生成中间信息的预测器，通过使用 多个移位量，以及通过使用临时信息生成信息的生成器。 生成粘滞位所需的循环时间被缩短以有效地生成粘性位，并且用于产生粘性位的硬件资源被减少。

公开(公告)号：US08554819B2

公开(公告)日：2013-10-08

申请号：US12461338

申请日：2009-08-07

申请人： Kunihiko Tajiri

发明人： Kunihiko Tajiri

IPC分类号： G06F7/485

CPC分类号： G06F7/49947 ,  G06F7/49915

摘要： A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.

摘要翻译： 在计算结果的舍入期间，计算处理器通过将计算结果递增1来输出是否产生进位输出。 计算处理器包括执行计算的计算单元; 移动量计算单元，计算所述计算结果的移动量; 归一化单元，其通过使用所述移位量来执行所述计算结果的归一化; 预测单元，当通过使用移位量将计算结果移位等于或大于预定移动量的量时，预测移位结果的预定区域中的每个位是否为1，与 正常化 以及检测单元，通过从归一化单元接收归一化结果和来自预测单元的预测结果来检测进位的产生。

公开(公告)号：US08392491B2

公开(公告)日：2013-03-05

申请号：US12827569

申请日：2010-06-30

申请人： Kunihiko Tajiri

发明人： Kunihiko Tajiri

IPC分类号： G06F15/00

CPC分类号： G06F5/015

摘要： A shift calculator including a first shifter includes a right shifter configured to perform a right shift of 0 to 3 bits and a left shifter configured to perform a left shift of 0 to 3 bits, on input data of which a data width is N bits, in accordance with left/right selection signals, based on a shift amount of 3 bits or smaller out of an input shift amount, a rotator configured to perform a right rotate shift of 0 to N−4 bits or a left rotate shift of 0 to N−4 bits, on output data from said first shifter, in accordance with said left/right selection signals, based on a shift amount of 4 bits or greater out of the input shift amount, and a mask unit configured to perform mask processing in 4-bit increments on output data from said rotator based on mask signals.

摘要翻译： 包括第一移位器的移位计算器包括被配置为执行0到3位的右移位的右移位器和被配置为对数据宽度为N位的输入数据执行0到3位的左移的左移位器， 根据左/右选择信号，基于输入移位量的3位或更小的移位量，旋转器被配置为执行0到N-4位的右旋转移位或者向左旋转移位0到 根据所述左/右选择信号，根据所述输入移位量中的4位或更大的移位量，对来自所述第一移位器的输出数据的N-4位，以及掩模单元，被配置为执行掩码处理 基于掩码信号，来自所述旋转器的输出数据的4位增量。

公开(公告)号：US20090300087A1

公开(公告)日：2009-12-03

申请号：US12461338

申请日：2009-08-07

申请人： Kunihiko Tajiri

发明人： Kunihiko Tajiri

IPC分类号： G06F7/38 ,  G06F7/00

CPC分类号： G06F7/49947 ,  G06F7/49915

摘要： A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.

摘要翻译： 在计算结果的舍入期间，计算处理器通过将计算结果递增1来输出是否产生进位输出。 计算处理器包括执行计算的计算单元; 移动量计算单元，计算所述计算结果的移动量; 归一化单元，其通过使用所述移位量来执行所述计算结果的归一化; 预测单元，当通过使用移位量将计算结果移位等于或大于预定移动量的量时，预测移位结果的预定区域中的每个位是否为1，与 正常化 以及检测单元，通过从归一化单元接收归一化结果和来自预测单元的预测结果来检测进位的产生。

公开(公告)号：US20110004643A1

公开(公告)日：2011-01-06

申请号：US12827569

申请日：2010-06-30

申请人： Kunihiko TAJIRI

发明人： Kunihiko TAJIRI

IPC分类号： G06F5/01

CPC分类号： G06F5/015

摘要： A shift calculator including a first shifter includes a right shifter configured to perform a right shift of 0 to 3 bits and a left shifter configured to perform a left shift of 0 to 3 bits, on input data of which a data width is N bits, in accordance with left/right selection signals, based on a shift amount of 3 bits or smaller out of an input shift amount, a rotator configured to perform a right rotate shift of 0 to N−4 bits or a left rotate shift of 0 to N−4 bits, on output data from said first shifter, in accordance with said left/right selection signals, based on a shift amount of 4 bits or greater out of the input shift amount, and a mask unit configured to perform mask processing in 4-bit increments on output data from said rotator based on mask signals.

摘要翻译： 包括第一移位器的移位计算器包括被配置为执行0到3位的右移位的右移位器和被配置为对数据宽度为N位的输入数据执行0到3位的左移的左移位器， 根据左/右选择信号，基于输入移位量的3位或更小的移位量，旋转器被配置为执行0到N-4位的右旋转移位或者向左旋转移位0到 根据所述左/右选择信号，根据所述输入移位量中的4位或更大的移位量，对来自所述第一移位器的输出数据的N-4位，以及掩模单元，被配置为执行掩码处理 基于掩码信号，来自所述旋转器的输出数据的4位增量。

公开(公告)号：US07720899B2

公开(公告)日：2010-05-18

申请号：US11385718

申请日：2006-03-22

申请人： Kunihiko Tajiri

发明人： Kunihiko Tajiri

IPC分类号： G06F7/38

CPC分类号： G06F5/012 ,  G06F7/483 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/5443 ,  G06F7/74 ,  G06F2207/382

摘要： An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit outputting the arithmetic operation result, a normalizer having a plurality of shifter normalizing the arithmetic operation result, a shift amount calculator calculating a plurality of shift amounts for the plural shifter, and a predictor generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator generating the information by using the interim information. The cycle time required to generate a sticky bit is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit is reduced.

摘要翻译： 算术运算部，生成表示算术运算结果归一化时算术运算结果是否移位的信息，具有输出算术运算结果的算术运算部，具有使运算结果归一化的多个移位器的归一化部 ，计算多个移位器的多个移位量的移位量计算器，以及作为在算术运算结果被归一化时算术运算结果是否移位的预测结果的预测器生成中间信息的预测器，通过使用 多个移位量，以及通过使用临时信息生成信息的生成器。 生成粘滞位所需的循环时间被缩短以有效地生成粘性位，并且用于产生粘性位的硬件资源被减少。