公开(公告)号：US6038371A

公开(公告)日：2000-03-14

申请号：US807507

申请日：1997-02-27

申请人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

发明人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

IPC分类号： H04N5/7826 ,  H04N5/783 ,  H04N9/804 ,  H04N9/82 ,  H04N5/92

CPC分类号： H04N9/8045 ,  H04N9/8042 ,  H04N5/78266 ,  H04N5/783 ,  H04N9/8227

摘要： A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on tracks of a prescribed recording medium and playbacks them, includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding them in variable length code, a data rearrangement canceller for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data rearrangment canceller.

摘要翻译： 一种可变长度代码记录/重放装置，其通过对帧内数据和可变长度码中的帧间数据进行编码，将它们作为记录代码记录在规定的记录介质的轨道上并进行重放，包括用于记录数据的数据重新排列器 在通过从编码为可变长度码的数据中重新排列规定数据来播放轨道上的至少两个特定速度模式播放的区域中，可变长度解码器，用于重放记录在记录介质上的数据并以可变长度解码它们 代码，用于在重排之前控制和恢复可变长度解码器的输出到原始数据序列的时间序列的数据重排消除器，以及用于在特定速度模式下从多个帧的解码输出构建重放图像的解码器 通过对该数据重排消除器的输出进行解码来回放。

公开(公告)号：US20110221961A1

公开(公告)日：2011-09-15

申请号：US13044421

申请日：2011-03-09

申请人： Kouichi KURIHARA

发明人： Kouichi KURIHARA

IPC分类号： H04J3/06 ,  H04N5/08

CPC分类号： H04N21/4302 ,  H04N5/08

摘要： According to an embodiment, a synchronization byte detection portion includes: an 0x47 detector configured to sequentially read in TS data in predetermined units from a memory storing TS data including predetermined synchronization data, and detect a predetermined synchronization byte; a counter configured to count a number of times the predetermined synchronization byte is detected by the 0x47 detector; and a determination instruction portion configured such that, in a case where after detecting an initial predetermined synchronization byte, the 0x47 detector reads in TS data at predetermined intervals and the 0x47 detector does not detect the predetermined synchronization byte at the predetermined intervals a predetermined number of times in succession, the determination instruction portion causes the 0x47 detector to sequentially read in TS data from next TS data after the initial predetermined synchronization byte.

摘要翻译： 根据实施例，同步字节检测部分包括：0x47检测器，被配置为从存储存储包括预定同步数据的TS数据的存储器中以预定单位依次读入TS数据，并检测预定的同步字节; 配置为对由0x47检测器检测到预定同步字节的次数进行计数的计数器; 以及确定指示部分，其被配置为使得在检测到初始预定同步字节之后，0x47检测器以预定间隔读取TS数据，并且0x47检测器以预定间隔检测预定同步字节预定数量的 连续的次数，确定指令部分使得0x47检测器在初始预定同步字节之后从下一个TS数据顺序地读取TS数据。

公开(公告)号：US5751893A

公开(公告)日：1998-05-12

申请号：US35755

申请日：1993-03-24

申请人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

发明人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

IPC分类号： H04N5/7826 ,  H04N5/783 ,  H04N9/804 ,  H04N9/82 ,  H04N5/917

CPC分类号： H04N9/8045 ,  H04N9/8042 ,  H04N5/78266 ,  H04N5/783 ,  H04N9/8227

摘要： A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

公开(公告)号：US6009230A

公开(公告)日：1999-12-28

申请号：US843609

申请日：1997-04-10

申请人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

发明人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

IPC分类号： H04N5/7826 ,  H04N5/783 ,  H04N9/804 ,  H04N9/82 ,  H04N5/91

CPC分类号： H04N9/8045 ,  H04N9/8042 ,  H04N5/78266 ,  H04N5/783 ,  H04N9/8227

摘要： An encoded data recording apparatus with high speed reproduction capability, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

摘要翻译： 具有高速再现能力的编码数据记录装置，其通过以可变长度码编码帧内数据和帧间数据，将它们记录在记录介质的轨道的规定位置上并将其重播，其中包括 数据重排器，用于通过从编码为可变长度码的数据重新排列规定的数据，在轨道上记录至少两个特定速度模式播放的区域中的数据;可变长度解码器，用于重放记录在记录介质上的数据 并且以可变长度码进行解码;数据恢复器，用于在重新布置之前控制和恢复可变长度解码器的输出到原始数据序列的时间序列;以及解码器，用于从解码的输出构造用于多个帧的重放图像 在特定的速度模式下通过解码该数据恢复器的输出进行播放。

公开(公告)号：US5862295A

公开(公告)日：1999-01-19

申请号：US588923

申请日：1996-01-19

申请人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

发明人： Kenji Shimoda ,  Shuji Abe ,  Kouichi Kurihara

IPC分类号： H04N5/7826 ,  H04N5/783 ,  H04N9/804 ,  H04N9/82 ,  H04N5/91 ,  H04N5/917

CPC分类号： H04N9/8045 ,  H04N9/8042 ,  H04N5/78266 ,  H04N5/783 ,  H04N9/8227

摘要： A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearrange for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

摘要翻译： 一种可变长度码记录/重放装置，其通过编码可变长度码中的帧内数据和帧间数据，将它们记录在记录介质的轨道的规定位置上，并将其重新播放，其中包括数据重排 通过从编码为可变长度码的数据中重新排列规定的数据，在轨道上记录要播放的至少两个特定速度模式播放的区域中的数据;可变长度解码器，用于重放记录在记录介质上的数据和解码 以可变长度码为单位的数据恢复器，用于在重排之前控制和恢复可变长度解码器的输出到原始数据序列的时间序列的数据恢复器，以及用于从解码输出中构建重放图像的解码器， 通过对该数据恢复器的输出进行解码的特定速度模式播放。

公开(公告)号：US5841475A

公开(公告)日：1998-11-24

申请号：US548487

申请日：1995-10-26

申请人： Kouichi Kurihara ,  Shuji Abe

发明人： Kouichi Kurihara ,  Shuji Abe

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50 ,  H04N7/32

CPC分类号： H04N19/577 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61

摘要： Encoding data are given to a variable-length decoding circuit and are decoded, and are given to a memory so as to be stored therein. The same data are read out from the memory, whereby decoding processing of the encoding data is executed twice within one frame period. Decoding data due to the twice decoding processings are stored in the memory at an output part thereof. Data of odd fields are read out in display order in the first half of the display period of one frame. Data of even fields are read out in display order in the latter half of the display period of one frame. Thus, even in case where restored image data of a B-picture are outputted in interlacing, a memory capacity can be reduced.

摘要翻译： 将编码数据提供给可变长度解码电路，并将其解码，并将其提供给存储器以便存储在其中。 从存储器读出相同的数据，由此在一个帧周期内执行编码数据的解码处理两次。 由于两次解码处理的数据解码在其输出部分存储在存储器中。 在一帧的显示周期的前半部分中，以显示顺序读出奇数场的数据。 在一帧的显示周期的后半部分中，以显示顺序读出偶数场的数据。 因此，即使在以交错方式输出B图像的恢复图像数据的情况下，也可以减小存储容量。

公开(公告)号：US20090213925A1

公开(公告)日：2009-08-27

申请号：US12388749

申请日：2009-02-19

申请人： Takeshi Inagaki ,  Kenji Tomizawa ,  Shinichi Oosawa ,  Kouichi Kurihara

发明人： Takeshi Inagaki ,  Kenji Tomizawa ,  Shinichi Oosawa ,  Kouichi Kurihara

IPC分类号： H04N7/26 ,  H04N5/06

CPC分类号： H04N21/23406 ,  H04N21/4263 ,  H04N21/4305 ,  H04N21/44004 ,  H04N21/442

摘要： A buffer control device is provided with a nearly flow detecting section, a vertical cycle control section and a vertical synchronization signal generating section. The nearly flow detecting section compares the amount of data accumulated in a buffer and predetermined thresholds and detects the result of the comparison as nearly overflow or nearly underflow. The vertical cycle control section adjusts the length of a vertical synchronization cycle according to the result of the comparison by the nearly flow detecting section. The vertical synchronization signal generating section generates a new vertical synchronization signal from the result of the adjustment by the vertical cycle control section.

摘要翻译： 缓冲控制装置具有近似流量检测部分，垂直周期控制部分和垂直同步信号产生部分。 近似流量检测部分将缓冲器中累积的数据量与预定阈值进行比较，并将比较结果检测为几乎溢出或接近下溢。 垂直周期控制部根据近似流量检测部的比较结果来调整垂直同步周期的长度。 垂直同步信号生成部根据垂直周期控制部的调整结果生成新的垂直同步信号。

公开(公告)号：US5946036A

公开(公告)日：1999-08-31

申请号：US780282

申请日：1997-01-08

申请人： Kouichi Kurihara ,  Shuji Abe ,  Shinji Yoda

发明人： Kouichi Kurihara ,  Shuji Abe ,  Shinji Yoda

IPC分类号： H03M7/00 ,  H04N19/00 ,  H04N19/423 ,  H04N19/426 ,  H04N19/46 ,  H04N19/503 ,  H04N19/59 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/80 ,  H04N19/85 ,  H04N19/91 ,  H04N7/12 ,  H04N9/64

CPC分类号： H04N19/427 ,  H04N19/423 ,  H04N19/61

摘要： A coding data is performed in decoding by a stream decoding circuit, an IDCT circuit and an MC circuit. An AGU stores decoding data from the MC circuit to a memory. Regarding the decoding data of a B picture, the AGU writes only the decoding data which are necessary for image display, to a B picture region. Thus, a room occurs in a memory capacity. It is possible to hold the decoding data of the B picture through 2 field periods of time. It is possible to read twice the same decoding data, for display processing. Thus, frame interpolation processing is made possible, and it is possible to obtain a magnified image having high image quality.

摘要翻译： 在通过流解码电路，IDCT电路和MC电路的解码中执行编码数据。 AGU将从MC电路的解码数据存储到存储器。 关于B图像的解码数据，AGU仅将图像显示所需的解码数据写入B图像区域。 因此，在存储器容量中发生房间。 可以通过2场时间段来保持B图像的解码数据。 可以读取相同解码数据的两倍，进行显示处理。 因此，可以进行帧内插处理，并且可以获得具有高图像质量的放大图像。

公开(公告)号：US5754243A

公开(公告)日：1998-05-19

申请号：US805721

申请日：1997-02-25

申请人： Kouichi Kurihara ,  Shuji Abe ,  Takeshi Inagaki ,  Shinji Yoda

发明人： Kouichi Kurihara ,  Shuji Abe ,  Takeshi Inagaki ,  Shinji Yoda

IPC分类号： H04N5/44 ,  H04N7/00 ,  H04N7/01 ,  H04N7/26 ,  H04N7/50

CPC分类号： H04N7/0122 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N7/007 ,  H04N7/0105 ,  H04N5/4401 ,  Y10S348/913

摘要： A read control circuit reads image data, which are stored in a decoding image memory, at a read speed m/n times a display speed. These image data are written to line memories by a write control circuit. A read-address control circuit reads the image data from the line memories at a display speed, and line data for a letter-box image are generated by multipliers and an adder. Specifically, the line data of m lines which are read from the decoding image memory are transformed to n lines so that a letter-box display is made possible. Thus, letter-box transformation processing is performed with less memory capacity without the use of a field memory.

摘要翻译： 读取控制电路以显示速度m / n的读取速度读取存储在解码图像存储器中的图像数据。 这些图像数据通过写入控制电路写入行存储器。 读地址控制电路以显示速度从行存储器读取图像数据，并且通过乘法器和加法器产生字母盒图像的行数据。 具体地说，将从解码图像存储器读出的m行的行数据变换为n行，使得可以进行信箱显示。 因此，在不使用场存储器的情况下，以较少的存储容量执行信箱变换处理。

公开(公告)号：US5311306A

公开(公告)日：1994-05-10

申请号：US914385

申请日：1992-07-17

申请人： Seiichi Tanaka ,  Takashi Koga ,  Kouichi Kurihara

发明人： Seiichi Tanaka ,  Takashi Koga ,  Kouichi Kurihara

IPC分类号： H04N9/77 ,  H04N5/14 ,  H04N9/78 ,  H04N9/79

CPC分类号： H04N5/144 ,  H04N9/78

摘要： A motion detecting circuit for a video signal processor having a filter arrangement for separating the video signal into the low and high frequency components, a first detecting circuit for detecting a low frequency luminance moving signal, a second detecting circuit for detecting a high frequency luminance moving signal, a third detecting circuit for detecting a chrominance moving signal, a first threshold circuit for generating a low band luminance motion digit signal, a second threshold circuit for generating a high band luminance motion digit signal, a control circuit coupled for generating a control signal in response to the low and high band luminance motion digit signals, a gate circuit for selectively transmitting the chrominance moving signal in response to the control signal and a selector for selectively outputting the one of the low frequency luminance moving signal and the chrominance moving signal having the high signal intensity.

摘要翻译： 一种用于视频信号处理器的运动检测电路，具有用于将视频信号分离成低频和高频分量的滤波器装置，用于检测低频亮度运动信号的第一检测电路，用于检测高频亮度移动的第二检测电路 信号，用于检测色度运动信号的第三检测电路，用于产生低频带亮度运动数字信号的第一阈值电路，用于产生高频带亮度运动数字信号的第二阈值电路，耦合以产生控制信号的控制电路 响应于低和高频带亮度运动数字信号，选择性地响应于控制信号传输色度运动信号的门电路和选择器，用于选择性地输出低频亮度运动信号和色度运动信号中的一个具有 信号强度高。