公开(公告)号：US5809039A

公开(公告)日：1998-09-15

申请号：US603502

申请日：1996-02-20

申请人： Toshiro Takahashi ,  Fumihiko Shirotori ,  Kaoru Moriwaki ,  Masahiko Nagai

发明人： Toshiro Takahashi ,  Fumihiko Shirotori ,  Kaoru Moriwaki ,  Masahiko Nagai

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/00 ,  G11C29/00

CPC分类号： G01R31/318505

摘要： A logic LSI is divided into a plurality of functional blocks, and an output portion of each functional block is provided with a buffer circuit with a scan function which can change a function of latching data by a control signal and a function of making an input signal pass intact. The buffer circuit is connected to a test exclusive bus and the test data can be entered directly to the buffer or read out of the buffer. Test patterns are generated in each functional block and diagnosis can be carried out in each functional block. When the functional block is used in other LSI, since the test patterns already generated can be utilized, the time required for generation of test patterns and for the test can be significantly reduced.

摘要翻译： 逻辑LSI被分成多个功能块，并且每个功能块的输出部分设置有具有扫描功能的缓冲电路，该扫描功能可以通过控制信号改变锁存数据的功能，并且具有使输入信号 传球完好无损。 缓冲电路连接到测试专用总线，测试数据可以直接输入缓冲区或读出缓冲区。 在每个功能块中产生测试模式，并且可以在每个功能块中进行诊断。 当在其他LSI中使用功能块时，由于可以利用已经产生的测试图案，所以可以显着地减少产生测试图案和测试所需的时间。

公开(公告)号：US4891773A

公开(公告)日：1990-01-02

申请号：US42233

申请日：1987-04-24

申请人： Kimio Ooe ,  Nobutaka Amano ,  Takashige Kubo ,  Kaoru Moriwaki

发明人： Kimio Ooe ,  Nobutaka Amano ,  Takashige Kubo ,  Kaoru Moriwaki

IPC分类号： G06F11/25 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.

摘要翻译： 在用于执行包括具有未知内部逻辑的电路的逻辑电路的逻辑模拟的逻辑模拟方法中，使用具有未知内部逻辑的电路本身。 使用由电路提供的中断操作将电路的内部状态设置为客观状态，此后，将输入信号值施加到电路以获得合成输出。 对于没有未知内部逻辑的其他逻辑电路，执行软件逻辑仿真。 在这种软件逻辑仿真期间，称为具有未知内部逻辑的实际电路。

公开(公告)号：US5184308A

公开(公告)日：1993-02-02

申请号：US591148

申请日：1990-10-01

申请人： Masahiko Nagai ,  Hiroo Watai ,  Takaharu Nagumo ,  Kaoru Moriwaki

发明人： Masahiko Nagai ,  Hiroo Watai ,  Takaharu Nagumo ,  Kaoru Moriwaki

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F11/25 ,  G06F11/26 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G06F11/261 ,  G06F17/5022

摘要： A logic circuit to be an object for fault simulation is logically modified into a logic circuit configuration using logic gates of a predetermined basic gate form. Pin management data indicative of a correspondence of pins of the logic gates to a position of fault assumption of each of the pins prior to logic modification is formed. Logic simulation is then performed by injecting a fault logic value into the position of fault assumption of each of the pins of the gate of the logic circuit subsequent to the logic modification corresponding to each of the pins prior to the logic modification with reference to the pin management data, thereby implementing a fault simulation for detecting the fault of the logic circuit.

摘要翻译： 作为故障仿真的对象的逻辑电路在逻辑上被修改为使用预定的基本门形式的逻辑门的逻辑电路配置。 形成指示逻辑门的引脚对应于逻辑修改之前的每个引脚的故障假定的位置的引脚管理数据。 然后通过将故障逻辑值注入逻辑电路的栅极的每个引脚的故障位置的位置之后执行逻辑模拟，该逻辑电路的逻辑修改对应于逻辑修改之前的每个引脚的参考引脚 管理数据，从而实现用于检测逻辑电路故障的故障模拟。

公开(公告)号：US4703257A

公开(公告)日：1987-10-27

申请号：US810296

申请日：1985-12-18

申请人： Takao Nishida ,  Toru Hiyama ,  Kaoru Moriwaki ,  Shun Ishiyama ,  Shunsuke Miyamoto

发明人： Takao Nishida ,  Toru Hiyama ,  Kaoru Moriwaki ,  Shun Ishiyama ,  Shunsuke Miyamoto

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/318536

摘要： A logic circuit having a diagnostic function is disclosed in which each of first latches for applying data to combinational circuits included in the logic circuit and/or receiving data from the combinational circuits is provided with a second latch and a selector for selecting the output of the first latch in a first mode and for selecting the output of the second latch in a second mode. In a regular operation, the output of the first latch is never transferred through the second latch, and the selector is operated in the first mode. Accordingly, the output of the first latch is supplied directly to a succeeding combinational circuit, and thus the delay caused by the second latch in the prior art can be eliminated. Although the delay caused by the selector is unavoidable, this delay can be made far smaller than the delay caused by the second latch. In a diagnostic operation, the output of the first latch is transferred through the second latch, and the selector is operated in the second mode, in order to perform the diagnostic operation stably even when data is transferred between first latches having the same phase, or the logic circuit includes a one-latch loop.

摘要翻译： 公开了一种具有诊断功能的逻辑电路，其中用于向包括在逻辑电路中的组合电路应用数据的第一锁存器和/或从组合电路接收数据中的每一个提供有第二锁存器和选择器，用于选择 第一锁存器处于第一模式并用于在第二模式中选择第二锁存器的输出。 在常规操作中，第一锁存器的输出不会通过第二锁存器传送，并且选择器在第一模式下操作。 因此，第一锁存器的输出被直接提供给后续组合电路，因此可以消除由现有技术中的第二锁存器引起的延迟。 虽然由选择器引起的延迟是不可避免的，但是该延迟可以远小于由第二锁存器引起的延迟。 在诊断操作中，第一锁存器的输出通过第二锁存器传送，并且选择器在第二模式下操作，以便即使在具有相同相位的第一锁存器之间传送数据时也可以稳定地执行诊断操作，或 逻辑电路包括单锁存环路。

公开(公告)号：US5856926A

公开(公告)日：1999-01-05

申请号：US599090

申请日：1996-02-07

申请人： Kazuhiko Matsumoto ,  Takao Shinsha ,  Nobuyuki Hayashi ,  Hiromoto Sakaki ,  Miyako Tandai ,  Yasunori Yamada ,  Takahiro Nakata ,  Kaoru Moriwaki ,  Junji Koshishita

发明人： Kazuhiko Matsumoto ,  Takao Shinsha ,  Nobuyuki Hayashi ,  Hiromoto Sakaki ,  Miyako Tandai ,  Yasunori Yamada ,  Takahiro Nakata ,  Kaoru Moriwaki ,  Junji Koshishita

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction. The system includes a logic input device for inputting an old logic, an old circuit generated from the old logic and optimized to satisfy the design constriction, and a new logic partially changing from the old logic file, a logic synthesizing device for generating a first intermediate circuit file from the new logic file, a discriminating device for discriminating a common sub-circuit of the old circuit having an equivalent logic function and an uncommon sub-circuit of the first intermediate circuit having an inconsistent logic function, from the old circuit and the first intermediate circuit, a circuit updating device for generating a second intermediate circuit file by merging the common sub-circuit of the old circuit and the uncommon sub-circuit of the first intermediate circuit, and an optimizing device for optimizing the uncommon sub-circuit of the second intermediate circuit so as to satisfy the design constriction.

摘要翻译： 一种用于从给定逻辑生成优化电路的增量逻辑合成系统，其中所述优化电路满足设计限制。 该系统包括用于输入旧逻辑的逻辑输入装置，从旧逻辑生成并被优化以满足设计限制的旧电路，以及从旧逻辑文件部分改变的新逻辑，用于产生第一中间件的逻辑合成装置 来自新逻辑文件的电路文件，鉴别装置，用于从旧电路和旧电路鉴别具有不一致逻辑功能的第一中间电路的等效逻辑功能和不常用子电路的旧电路的公共子电路， 第一中间电路，用于通过合并旧电路的公共子电路和第一中间电路的不常用子电路来产生第二中间电路文件的电路更新装置，以及用于优化第一中间电路的不常用子电路的优化装置 第二中间电路，以满足设计收缩。