公开(公告)号：US07871884B2

公开(公告)日：2011-01-18

申请号：US12195365

申请日：2008-08-20

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L29/66181

Abstract: A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure.

Abstract translation: 一种用于制造DRAM的方法包括首先提供形成图案化的第一掩模层和被图案化的第一掩模层暴露的深沟槽的衬底。 深沟槽电容器形成在深沟槽中，并且每个深沟槽电容器包括下电极，上电极和电容器介电层。 在第一掩模层和衬底中形成器件隔离层，用于限定有源区。 去除第一掩模层以暴露衬底，并且在暴露的衬底上形成半导体层。 图案化半导体层和衬底以形成沟槽，并且沟槽的底部与沟槽电容器的上部电极相邻。 填充到沟槽中的栅极结构形成在衬底上。 掺杂区域形成在与栅极结构的一侧相邻的衬底中。

公开(公告)号：US07582524B2

公开(公告)日：2009-09-01

申请号：US11529502

申请日：2006-09-29

Applicant: Jung Wu Chien ,  Chia Shun Hsiao

Inventor： Jung Wu Chien ,  Chia Shun Hsiao

IPC: H01L21/8242

CPC classification number: H01L27/105 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.

Abstract translation: 一种用于制备存储器结构的方法包括以下步骤：在衬底的电介质结构上形成多个线状块，并形成露出线状块的侧壁的第一蚀刻掩模。 除去包含第一蚀刻掩模的线状块的一部分以减小线状块的宽度，以形成包括以隔行方式布置的多个第一块和第二块的第二蚀刻掩模。 随后，去除未被第二蚀刻掩模覆盖的介电结构的一部分，以在电介质结构中形成多个开口，并且在每个开口中形成导电插塞。 多个开口包括位于第一块之间的第一开口和位于第二块之间的第二开口，并且第一开口和第二开口延伸到有源区域的相对侧。

公开(公告)号：US07479452B2

公开(公告)日：2009-01-20

申请号：US11104213

申请日：2005-04-12

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76897 ,  H01L27/10885 ,  H01L27/10894

Abstract: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

Abstract translation: 在本发明中公开了一种形成电池位线接触插塞的方法。 在提供具有第一区域和第二区域的半导体衬底之后，在第一区域形成单元位线触点。 在第二区域形成位线图形开口之后，在单元位线触点和位线图形开口的侧壁上形成多个间隔物。 然后在第二区域的开口内形成衬底接触和栅极接触。 通过进行蚀刻工艺在每个基板接触和栅极接触之间形成沟槽之后，形成电池 - 位线接触插塞，基板接触插塞和栅极接触插头。

公开(公告)号：US20080138970A1

公开(公告)日：2008-06-12

申请号：US11670427

申请日：2007-02-02

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/28

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66583

Abstract: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.

公开(公告)号：US20060234441A1

公开(公告)日：2006-10-19

申请号：US11222966

申请日：2005-09-12

Applicant: Jung Wu Chien ,  Tsai Nieh ,  Ju Cheng Chen ,  Chao Hsi Chung

Inventor： Jung Wu Chien ,  Tsai Nieh ,  Ju Cheng Chen ,  Chao Hsi Chung

IPC: H01L21/465 ,  H01L21/8242

CPC classification number: H01L21/0273 ,  B82Y10/00 ,  H01L21/31116 ,  H01L21/31625 ,  H01L27/10861 ,  H01L28/84 ,  H01L29/66181

Abstract: A method for preparing a deep trench first forms a trench in a semiconductor substrate and a stacked structure in the trench, wherein the stacked structure includes at least one nitrogen-containing layer. A phosphorous oxide layer is then formed on the surface of the nitrogen-containing layer. The phosphorous oxide is then transformed into an etchant in a steam atmosphere to remove the nitrogen-containing layer in the trench. The phosphorous oxide layer in the trench is then removed, and the nitrogen-containing layer can be effectively removed. The method further comprises forming a plurality of crystallites on a portion of the nitrogen-containing layer before the phosphorous oxide layer is formed on the surface of the nitrogen-containing layer, which allows the formation of a deep trench with a rough inner sidewall.

Abstract translation: 用于制备深沟槽的方法首先在半导体衬底中形成沟槽，并在沟槽中形成堆叠结构，其中堆叠结构包括至少一个含氮层。 然后在含氮层的表面上形成磷氧化物层。 然后将氧化磷在蒸汽气氛中转化成蚀刻剂以除去沟槽中的含氮层。 然后去除沟槽中的磷氧化物层，并且可以有效地去除含氮层。 该方法还包括在含氮层的表面上形成含氮层的一部分之前形成多个微晶，这允许形成具有粗糙内侧壁的深沟槽。

公开(公告)号：US07098100B1

公开(公告)日：2006-08-29

申请号：US11114152

申请日：2005-04-26

Applicant: Hui Min Li ,  Jung Wu Chien ,  Chao Hsi Chung ,  Ming Hung Lin

Inventor： Hui Min Li ,  Jung Wu Chien ,  Chao Hsi Chung ,  Ming Hung Lin

IPC: H01L21/8234

CPC classification number: H01L29/66181 ,  H01L27/10861

Abstract: The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom electrode, a top electrode positioned on the dielectric layer, a collar oxide layer positioned on an upper inner surface of the trench, a buried conductive strap positioned on the top electrode, and an interface layer made of silicon nitride positioned at the side of the buried conductive strap. The bottom electrode, the dielectric layer and the top electrode form a capacitive structure. The collar oxide layer includes a first block and a second block, and the height of the first block is larger than the height of the second block. The interface layer is positioned on a portion of the inner surface of the trench above the second block.

Abstract translation: 本发明公开了一种在半导体衬底的沟槽中形成的沟槽电容器。 所述沟槽电容器包括位于所述沟槽的下外表面上的底电极，位于所述底电极的内表面上的电介质层，位于所述电介质层上的顶电极，位于所述电介质层的上内表面上的环状氧化物层 沟槽，位于顶部电极上的埋入导电带，以及位于掩埋导电带侧面的由氮化硅制成的界面层。 底部电极，电介质层和顶部电极形成电容结构。 环状氧化物层包括第一块和第二块，并且第一块的高度大于第二块的高度。 界面层位于第二块上方的沟槽的内表面的一部分上。

公开(公告)号：US07348622B2

公开(公告)日：2008-03-25

申请号：US11445847

申请日：2006-06-02

Applicant: Chao-Hsi Chung ,  Jung-Wu Chien

Inventor： Chao-Hsi Chung ,  Jung-Wu Chien

IPC: H01L31/119

CPC classification number: H01L27/1087 ,  H01L27/10867

Abstract: A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

Abstract translation: 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US20080044970A1

公开(公告)日：2008-02-21

申请号：US11516627

申请日：2006-09-07

Applicant: Jung Wu Chien ,  Chia Shun Hsiao

Inventor： Jung Wu Chien ,  Chia Shun Hsiao

IPC: H01L21/8244 ,  H01L21/8234

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10855

Abstract: A memory structure comprises a semiconductor substrate, an active are positioned in the semiconductor substrate, a plurality of doped regions positioned in the semiconductor substrate, a first conductive plug connecting a bit line and one of the doped regions and a second conductive plug connecting a capacitor and another one of doped regions. The first conductive plug includes a first block positioned in the active area and a second block positioned at a first side of the active area, and the bit line electrically connects the second block. The second conductive plug includes a third block positioned in the active area and a fourth block positioned at a second side of the active area, and the capacitor electrically connects the fourth block. The first side of the active area is opposite to the second side of the active area.

Abstract translation: 存储器结构包括半导体衬底，有源层位于半导体衬底中，位于半导体衬底中的多个掺杂区，连接位线和一个掺杂区的第一导电插塞和连接电容器的第二导电插头 和另一个掺杂区域。 第一导电插塞包括位于有源区域中的第一块和位于有源区的第一侧的第二块，并且位线电连接第二块。 第二导电插塞包括位于有源区域中的第三块和位于有源区的第二侧的第四块，并且电容器电连接第四块。 有源区域的第一侧与有源区域的第二侧相反。

公开(公告)号：US07232719B2

公开(公告)日：2007-06-19

申请号：US11092150

申请日：2005-03-28

Applicant: Chao-Hsi Chung ,  Jung-Wu Chien

Inventor： Chao-Hsi Chung ,  Jung-Wu Chien

IPC: H01L21/8242

CPC classification number: H01L27/1087 ,  H01L27/10867

Abstract: A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

Abstract translation: 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US20070085152A1

公开(公告)日：2007-04-19

申请号：US11250822

申请日：2005-10-14

Applicant: Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

Inventor： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC: H01L29/76

CPC classification number: H01L27/10867 ,  H01L27/0207

Abstract: A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

Abstract translation: 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。