Arithmetic and logic unit using half adder
    4.
    发明授权
    Arithmetic and logic unit using half adder 失效
    使用半加法器的算术和逻辑单元

    公开(公告)号:US07376691B2

    公开(公告)日:2008-05-20

    申请号:US10849665

    申请日:2004-05-20

    IPC分类号: G06F7/50

    CPC分类号: G06F7/57

    摘要: The present invention discloses an ALU (Arithmetic Logic Unit) that can be operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using a half adder that uses a superconductor rapid single flux quantum logic device. The ALU using a half adder includes a half adder using a superconductor rapid single flux quantum logic device as a logic circuit, and a switching unit that has input ports respectively connected to a sum output port and a carry output port of the half adder and is operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using output signals of the half adder. The switching unit includes a first switch having an input port connected to the sum output port of the half adder, a second switch having an input port connected to the carry output port of the half adder and an output port connected to an output port of the first switch, and a third switch having an input port connected to the carry output port of the half adder.

    摘要翻译: 本发明公开了一种ALU(算术逻辑单元),其可以使用使用超导体快速单通量量子逻辑器件的半加法器作为或门,与门,加法器门和异或门来操作。 使用半加法器的ALU包括使用超导体快速单通量量子逻辑器件作为逻辑电路的半加法器,以及具有分别连接到半加法器的和输出端口和进位输出端口的输入端口的开关单元,并且是 作为或门,与门,加法器门和使用半加法器的输出信号的异或门运算。 开关单元包括具有连接到半加法器的和输出端口的输入端口的第一开关,具有连接到半加法器的进位输出端口的输入端口的第二开关和连接到半加法器的输出端口的输出端口 第一开关和具有连接到半加法器的进位输出端口的输入端口的第三开关。