公开(公告)号：US09396988B2

公开(公告)日：2016-07-19

申请号：US14703556

申请日：2015-05-04

Applicant: Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

Inventor： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/70 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76843 ,  H01L2221/1063

Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Abstract translation: 一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成 包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案， 衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

公开(公告)号：USRE42592E1

公开(公告)日：2011-08-02

申请号：US12886849

申请日：2010-09-21

Applicant: Jong-Sam Kim

Inventor： Jong-Sam Kim

IPC: H01M10/44

CPC classification number: H01M10/46 ,  H01M10/613 ,  H01M10/623 ,  H01M10/6551 ,  H01M10/667 ,  H02J7/0068

Abstract: A rechargeable battery pack for portable electronic equipment is includes a battery coupled to a charge/discharge circuit and includes a a first substrate for mounting parts positioned on a high-current path and a second substrate for mounting peripheral circuits for controlling a charge/discharge of the battery. Accordingly, heat sensitive parts on low current paths may be thermally isolated from heat generating parts on high current paths.

Abstract translation: 用于便携式电子设备的可再充电电池组包括耦合到充电/放电电路的电池，并且包括用于安装位于大电流路径上的部件的第一基板和用于安装外围电路的第二基板，用于控制所述充电/ 电池。 因此，在低电流路径上的热敏部件可以在高电流路径上与发热部件热隔离。

公开(公告)号：US20090231022A1

公开(公告)日：2009-09-17

申请号：US12327729

申请日：2008-12-03

Applicant: Jong Sam Kim ,  Jong Chern Lee

Inventor： Jong Sam Kim ,  Jong Chern Lee

IPC: G05F1/10

CPC classification number: G11C11/4085 ,  G11C5/145 ,  G11C11/4074 ,  H02M3/073 ,  H02M2003/077

Abstract: A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump.

Abstract translation: 一种半导体存储装置的泵浦电压产生电路，所述泵送电压产生电路包括：检测单元，被配置为将泵浦电压的电平与参考电压的电平进行比较以产生检测信号;振荡信号发生器，被配置为顺序地产生 响应于所述检测信号的第一振荡信号和第二振荡信号，并且当产生所述第二振荡信号时提升所述第一和第二振荡信号的频率;第一泵，被配置为响应于所述第一振荡 信号，以及第二泵，被配置为响应于所述第二振荡信号执行泵送操作，其中所述第一泵和所述第二泵的输出端子共同连接，并且所述泵浦电压在所述第一泵的输出端子处输出， 第二个泵。

公开(公告)号：US07583060B2

公开(公告)日：2009-09-01

申请号：US11219520

申请日：2005-09-02

Applicant: Jong Sam Kim

Inventor： Jong Sam Kim

IPC: H02J7/00 ,  H02H3/00

CPC classification number: H02J7/0026 ,  H02H7/18 ,  H02J7/0021

Abstract: A protective circuit for a secondary battery pack advantageously having a simple circuit configuration while maintaining the safety of banks in the circuit. Each protective circuit has banks adapted to be charged or to discharge voltage, each bank being coupled to a controller that senses the charging or discharging voltage of the bank and outputs a predetermined value if overcharging or over-discharging is sensed. A level shifter is adapted to shift the voltage output from the controller to an adjusted voltage approximately equal to the voltage output from one of the other controllers. A switching means controls the stopping of charging or discharging of the banks.

Abstract translation: 一种用于二次电池组的保护电路，其有利地具有简单的电路配置，同时保持电路中的组的安全性。 每个保护电路具有适于充电或放电电压的组，每个组耦合到感测组的充电或放电电压的控制器，并且如果感测到过充电或过放电，则输出预定值。 电平移位器适于将从控制器输出的电压移动到大约等于从其他控制器之一输出的电压的调整电压。 切换装置控制银行的充电或放电停止。

公开(公告)号：US07271958B2

公开(公告)日：2007-09-18

申请号：US11347636

申请日：2006-02-02

Applicant: Sang Kee Yoon ,  Jong Sam Kim

Inventor： Sang Kee Yoon ,  Jong Sam Kim

IPC: G02B5/18

CPC classification number: G02B26/0808

Abstract: The present invention relates to diffractive light modulators and, more particularly, to a diffractive light modulator in which the lower support for mirrors is configured in consideration of the internal intrinsic stress of a mirror, thus improving the flatness of a mirror surface and enhancing the optical efficiency of the light modulator.

Abstract translation: 本发明涉及衍射光调制器，更具体地说，涉及一种衍射光调制器，其中考虑到反射镜的内部固有应力来构造反射镜的下支撑件，从而提高了镜面的平坦度并增强了光学 光调制器的效率。

公开(公告)号：US20160079115A1

公开(公告)日：2016-03-17

申请号：US14703556

申请日：2015-05-04

Applicant: Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

Inventor： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76843 ,  H01L2221/1063

Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Abstract translation: 一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成 包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案， 衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

公开(公告)号：US20110050271A1

公开(公告)日：2011-03-03

申请号：US12941874

申请日：2010-11-08

Applicant: Jong Sam Kim ,  Kwang Jun Cho

Inventor： Jong Sam Kim ,  Kwang Jun Cho

IPC: G01R31/26

CPC classification number: G01R31/31908

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract translation: 测试装置包括测试熔丝单元，用于在测试时间期间响应于测试模式信号产生测试熔丝信号，并且在测试时间终止之后根据熔丝切割生成测试熔丝信号;组合信号产生单元，用于 当测试模式信号被激活时，存储测试信号和停止组合信号，并且当测试模式信号被激活时输出存储的测试信号作为组合信号;以及代码信号产生单元，用于当测试模式信号被激活时激活测试代码信号 测试熔丝信号和组合信号被激活。

公开(公告)号：US5920422A

公开(公告)日：1999-07-06

申请号：US767005

申请日：1996-12-17

Applicant: Jong-Sam Kim

Inventor： Jong-Sam Kim

IPC: G02F1/015 ,  G02B5/08 ,  G02B26/08 ,  G02B26/00

CPC classification number: G02B26/0858

Abstract: A method for manufacturing an array of thin film actuated mirrors capable of ensuring an optimum optical efficiency is disclosed. The method includes the steps of: forming a thin film sacrificial layer on top of an active matrix; forming an array of semifinished actuating structures on top of the thin film sacrificial layer, wherein each of the semifinished actuating structures includes a thin film electrodisplacive member, a second thin film electrode and an elastic member; forming selectively a polymer layer; depositing a first thin film layer on top of each of the semifinished actuating structures; removing the polymer layer, thereby forming an array of actuating structures, each of the actuating structures having a first thin film electrode and the semifinished actuating structure; and removing the thin film sacrificial layer, thereby forming the array of thin film actuated mirrors. Since the formation of the array of semifinished actuating structures is followed by the formation of the first thin film electrode, it may prevent the first thin film electrode, which also functions as a mirror, from chemically or physically damaged during the formation of the array of semifinished actuating structures, thereby ensuring the optical efficiency of the array of thin film actuated mirrors.

Abstract translation: 公开了一种用于制造能够确保最佳光学效率的薄膜致动反射镜阵列的方法。 该方法包括以下步骤：在有源矩阵的顶部上形成薄膜牺牲层; 在所述薄膜牺牲层的顶部上形成半成品致动结构的阵列，其中所述半成品致动结构中的每一个包括薄膜电致位移元件，第二薄膜电极和弹性元件; 选择性地形成聚合物层; 在每个半成品致动结构的顶部上沉积第一薄膜层; 去除聚合物层，由此形成致动结构的阵列，每个致动结构具有第一薄膜电极和半成品致动结构; 并去除薄膜牺牲层，从而形成薄膜致动反射镜阵列。 由于形成半导体致动结构的阵列之后是第一薄膜电极的形成，所以可以防止在形成阵列阵列期间化学或物理损坏的第一薄膜电极也起着反射镜的作用 半致动致动结构，从而确保薄膜致动反射镜阵列的光学效率。

公开(公告)号：US08253480B2

公开(公告)日：2012-08-28

申请号：US12829900

申请日：2010-07-02

Applicant: Jong-Sam Kim

Inventor： Jong-Sam Kim

IPC: G05F1/10

CPC classification number: G11C5/14

Abstract: An internal voltage control circuit includes active drivers, a control unit, and a time interval adjustment unit. The active drivers are configured to receive a common internal voltage. The control unit is configured to control respective enable operations of the active drivers. The time interval adjustment unit is configured to respectively supply enable signals, generated by the control unit, to the active drivers at respective predetermined time intervals.

Abstract translation: 内部电压控制电路包括主动驱动器，控制单元和时间间隔调整单元。 有源驱动器配置为接收公共内部电压。 控制单元被配置为控制主动驱动器的相应启用操作。 时间间隔调整单元被配置为分别以各自的预定时间间隔将由控制单元产生的使能信号提供给有效驱动器。

公开(公告)号：US08149639B2

公开(公告)日：2012-04-03

申请号：US12941874

申请日：2010-11-08

Applicant: Jong-Sam Kim ,  Kwang-Jun Cho

Inventor： Jong-Sam Kim ,  Kwang-Jun Cho

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G01R31/31908

Abstract: A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.

Abstract translation: 测试装置包括测试熔丝单元，用于在测试时间期间响应于测试模式信号产生测试熔丝信号，并且在测试时间终止之后根据熔丝切割生成测试熔丝信号;组合信号产生单元，用于 当测试模式信号被激活时，存储测试信号和停止组合信号，并且当测试模式信号被激活时输出存储的测试信号作为组合信号;以及代码信号产生单元，用于当测试模式信号被激活时激活测试代码信号 测试熔丝信号和组合信号被激活。