公开(公告)号：US20080182360A1

公开(公告)日：2008-07-31

申请号：US11907137

申请日：2007-10-10

申请人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

发明人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

IPC分类号： H01L21/60

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/81801 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a semiconductor package is applied to fabricate the package with the lead frame. The fabrication method includes: performing a surface treatment on a carrier; electroplating a plurality of metal-stacked layers on the surface of the carrier, wherein the top of the metal-stacked layer is a bonding surface and the bottom of the metal-stacked layer is a welding surface; performing a chip bonding step; forming a molding compound on the carrier; removing the carrier and performing a dicing step to form a plurality of semiconductor packages. The fabrication method of a semiconductor package also includes that forming a plurality of cavities on the carrier surface, electroplating the metal-stacked layer on the cavities, and then performing the chip bonding step, forming the molding compound on the carrier; remove the carrier and performing the dicing step. Using the foregoing steps can prevent the overflow situation without using any tape.

摘要翻译： 应用半导体封装的制造方法来制造具有引线框架的封装。 制造方法包括：对载体进行表面处理; 在载体的表面上电镀多个金属堆叠层，其中金属堆叠层的顶部是接合表面，金属堆叠层的底部是焊接表面; 执行芯片接合步骤; 在载体上形成模塑料; 移除载体并执行切割步骤以形成多个半导体封装。 半导体封装的制造方法还包括在载体表面上形成多个空腔，将金属堆叠层电镀在空腔上，然后进行芯片接合步骤，在载体上形成模塑料; 移除载体并执行切割步骤。 使用上述步骤可以防止溢出情况而不使用任何磁带。

公开(公告)号：US08013434B2

公开(公告)日：2011-09-06

申请号：US12128163

申请日：2008-05-28

申请人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

发明人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

IPC分类号： H01L33/00

CPC分类号： H01L23/3735 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L33/486 ,  H01L33/60 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/181 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83851 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention discloses a package substrate comprising an insulative carrier having a through-hole penetrating the top and bottom surfaces thereof; at least one first and second conductive layers comprising circuits respectively formed on the top and bottom surfaces and covering an opening of the through-hole; a conductive element set in the through-hole for electrically connecting the first and second conductive layers; a first metal layer formed on the first and/or the second conductive layer; and at least one chip receiving bay formed by removing a portion of the carrier from the upper to the lower surfaces until the second conductive layer is exposed for accommodating at least one chip therein on the exposed second conductive layer. The package structure has a reduced overall thickness and an enhanced heat-dissipation effect for the chip and prevents from humidity penetration. A manufacturing method for the package structure is also disclosed.

摘要翻译： 本发明公开了一种封装基板，包括：绝缘载体，具有穿透其顶表面和底表面的通孔; 至少一个第一和第二导电层，包括分别形成在顶表面和底表面上并覆盖通孔的开口的电路; 设置在所述通孔中用于电连接所述第一和第二导电层的导电元件; 形成在第一和/或第二导电层上的第一金属层; 以及通过从上到下表面去除载体的一部分直到第二导电层被暴露以在暴露的第二导电层上容纳其中的至少一个芯片而形成的至少一个芯片接收间隔。 封装结构具有减小的总体厚度和增强的芯片散热效果并防止湿度渗透。 还公开了一种用于封装结构的制造方法。

公开(公告)号：US20080315239A1

公开(公告)日：2008-12-25

申请号：US12128163

申请日：2008-05-28

申请人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

发明人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

IPC分类号： H01L33/00 ,  H01L23/48 ,  H05K3/42

CPC分类号： H01L23/3735 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L33/486 ,  H01L33/60 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/181 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83851 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention discloses a manufacture method for a thin double-sided package substrate, which includes steps: providing a carrier; respectively forming a first conductive layer and a second conductive layer on the upper and lower surfaces of the carrier; forming a through-hole penetrating the first conductive layer and the carrier but not penetrating the second conductive layer; setting a conductive element in the through-hole to electrically connect the first conductive layer with the second conductive layer; forming desired circuits on the first conductive layer and/or the second conductive layer; forming a first metal layer on the first conductive layer and/or the second conductive layer; and removing the carrier located in a predetermined region to form a chip receiving bay. The present invention also discloses a package substrate made by the abovementioned manufacture method, which can reduce the overall thickness of a chip package structure, increase the heat-dissipation effect of the chip and prevent the chip package structure from humidity penetration.

摘要翻译： 本发明公开了一种薄双面封装基板的制造方法，其特征在于，包括：提供载体; 分别在所述载体的上表面和下表面上形成第一导电层和第二导电层; 形成穿过第一导电层和载体但不穿透第二导电层的通孔; 在所述通孔中设置导电元件以将所述第一导电层与所述第二导电层电连接; 在第一导电层和/或第二导电层上形成所需的电路; 在第一导电层和/或第二导电层上形成第一金属层; 并且移除位于预定区域中的载体以形成芯片接收槽。 本发明还公开了通过上述制造方法制造的封装衬底，其可以减小芯片封装结构的总体厚度，增加芯片的散热效果并防止芯片封装结构湿度渗透。

公开(公告)号：US20090294952A1

公开(公告)日：2009-12-03

申请号：US12128107

申请日：2008-05-28

申请人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

发明人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

IPC分类号： H01L23/04 ,  H01L21/02 ,  H01L21/44

CPC分类号： H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The present invention discloses a chip package carrier and a fabrication method, which have the advantages of high reliability, thickness reduction and the scale reduction. The carrier and the method uses blind holes., which penetrates the substrate but external traces and external bonding pads, which cover the external traces. A chip can be installed and encapsulated directly on a first surface.

摘要翻译： 本发明公开了一种芯片封装载体和制造方法，其具有可靠性高，厚度减小和刻度缩小的优点。 载体和方法使用盲孔，其穿透基板，但外部迹线和外部接合焊盘覆盖外部迹线。 芯片可以直接安装和封装在第一个表面上。

公开(公告)号：US20080135939A1

公开(公告)日：2008-06-12

申请号：US12000021

申请日：2007-12-07

申请人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

发明人： Chi Chih Lin ,  Bo Sun ,  Hung Jen Wang ,  Jen Feng Tseng

IPC分类号： H01L23/62

CPC分类号： H01L21/4821 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/85001 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85439 ,  H01L2224/85447 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A fabrication method of semiconductor and a structure thereof are disclosed herein. The present invention includes: providing a substrate; disposing a mask on the substrate, wherein the mask has a plurality of patterned openings to expose portions of the substrate; forming a metal layer on the exposed portions of the substrate; forming a surface treatment layer on the metal layer; removing the mask; performing a chip package step; and removing the substrate and the metal layer to form a height difference of semiconductor package with pads. The characteristic of the height difference not only can increase the thickness of the solder materials but also can easily check the soldering status.

摘要翻译： 本文公开了半导体的制造方法及其结构。 本发明包括：提供基板; 在衬底上设置掩模，其中所述掩模具有多个图案化的开口以暴露所述衬底的部分; 在所述基板的暴露部分上形成金属层; 在所述金属层上形成表面处理层; 去除面膜; 执行芯片封装步骤; 以及去除衬底和金属层以形成具有焊盘的半导体封装的高度差。 高差的特点不仅可以增加焊料的厚度，而且可以方便地检查焊接状态。