-
1.发明授权公开(公告)号：US09558131B1
公开(公告)日：2017-01-31
申请号：US13164426
申请日：2011-06-20
申请人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
发明人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/1678 , G06F13/1684 , G06F13/4022
摘要： An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.
摘要翻译： 一种IC，包括第一存储器控制器，第二存储器控制器和耦合到第一存储器控制器的第一接合电路，其中第一接合电路是硬逻辑接合电路，并且可操作以协调第一存储器控制器的存储器控制功能 和第二存储器控制器。 在一个实现中，第一存储器控制器是N位宽存储器控制器，第二存储器控制器是M位宽存储器控制器，并且第一接合电路可操作以协调第一存储器控制器和第二存储器的存储器控制功能 控制器，使得第一和第二存储器控制器一起用作N + M位宽存储器控制器，其中N和M是正整数。
-
2.发明授权Systems and methods for providing memory controllers with memory access request merging capabilities 有权为存储器控制器提供存储器访问请求合并功能的系统和方法公开(公告)号：US09032162B1
公开(公告)日：2015-05-12
申请号：US13209137
申请日：2011-08-12
申请人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
发明人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G06F13/161
摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.
摘要翻译： 集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控制器。 主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。 存储器控制器可以将存储器访问请求放置在队列中以实现。 存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。 合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。 存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。
-
公开(公告)号：US09343124B1
公开(公告)日：2016-05-17
申请号：US13194842
申请日：2011-07-29
CPC分类号： G11C7/1075 , G06F12/0853
摘要： A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.
摘要翻译： 公开了一种用于操作多端口存储器系统的方法和系统。 存储器控制器可以通过从外部存储器访问所请求的数据并将其传送到请求存储器端口来服务读取请求以供由耦合到存储器端口的设备访问。 如果与请求设备相关联的缓冲器已满，则可以使用存储器控制器的共享存储器临时存储数据。 为了减少较慢的存储器端口占用共享存储器并导致更快的存储器端口不足的能力，存储器控制器可以有利地调节或限制以更慢的时钟频率操作的存储器端口发出读取请求。 存储器端口可以基于每个存储器端口的至少一个相应属性，外部存储器的至少一个属性等彼此独立地被调整。
-
公开(公告)号：US09244867B1
公开(公告)日：2016-01-26
申请号：US13151123
申请日：2011-06-01
摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have predetermined bit widths. To provide the memory controller with adjustable port widths, a mapping interface may be provided that interfaces between master processing modules and the memory controller. The mapping interface may allocate port resources such as read data ports and write data ports of the memory controller to each master processing module. The mapping interface may assign a desirable number of read data ports and write data ports to each master to accommodate the requirements of that master. The mapping interface may assign a command port to each master that receives memory access requests from that master. The mapping interface may convey write acknowledgements in response to fulfilling write access requests.
摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控制器。 存储器控制器可以经由具有预定位宽的端口从主机接收存储器访问请求。 为了向存储器控制器提供可调整的端口宽度，可以提供在主处理模块和存储器控制器之间进行接口的映射接口。 映射接口可以向每个主处理模块分配诸如读数据端口和存储器控制器的写数据端口的端口资源。 映射界面可以分配理想数量的读取数据端口并将数据端口写入每个主机以适应该主机的要求。 映射接口可以向从主机接收存储器访问请求的每个主机分配一个命令端口。 响应于满足的写访问请求，映射界面可以传送写确认。
-
5.发明授权Systems and methods for providing memory controllers with scheduler bypassing capabilities 有权为内存控制器提供调度器旁路功能的系统和方法公开(公告)号：US08930641B1
公开(公告)日：2015-01-06
申请号：US13160384
申请日：2011-06-14
CPC分类号： G06F13/28
摘要： An integrated circuit may have a memory controller that interfaces between master processing modules and system memory. A scheduling module may be used to handle memory access requests received from multiple master modules. The scheduling module may arrange the received memory access requests in an order for fulfillment with system memory. A bypass module may be used to provide a low latency bypass path that allows memory access requests to bypass the scheduling module. The bypass module may include an eligibility detection module that identifies memory access requests eligible for scheduler bypassing, a port selection module that provides a low latency bypass path for the eligible memory access requests, multiplexing circuitry that selects between memory access requests provided from the low latency bypass path and from the output of the scheduling module, and a masking module that prevents redundant fulfillment of memory access requests.
摘要翻译： 集成电路可以具有在主处理模块和系统存储器之间进行接口的存储器控制器。 调度模块可用于处理从多个主模块接收到的存储器访问请求。 调度模块可以以系统存储器的顺序来排列所接收的存储器访问请求。 旁路模块可用于提供允许存储器访问请求绕过调度模块的低延迟旁路路径。 旁路模块可以包括标识符合调度器旁路的存储器访问请求的资格检测模块，为合格存储器访问请求提供低延迟旁路路径的端口选择模块，从低延迟提供的存储器访问请求之间进行选择的复用电路 旁路路径和调度模块的输出，以及防止冗余实现存储器访问请求的掩蔽模块。
-
6.发明授权公开(公告)号：US09208109B2
公开(公告)日：2015-12-08
申请号：US13151101
申请日：2011-06-01
CPC分类号： G06F13/1626 , G06F13/16 , G06F13/1605 , G06F13/18
摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控制器。 存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。 为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。 优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。 优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。
-
公开(公告)号：US20220405453A1
公开(公告)日：2022-12-22
申请号：US17854341
申请日：2022-06-30
申请人： Rahul Pal , Ashish Gupta , Navid Azizi , Jeffrey Schulz , Yin Chong Hew , Thuyet Ngo , George Chong Hean Ooi , Vikrant Kapila , Kok Kee Looi
发明人： Rahul Pal , Ashish Gupta , Navid Azizi , Jeffrey Schulz , Yin Chong Hew , Thuyet Ngo , George Chong Hean Ooi , Vikrant Kapila , Kok Kee Looi
摘要： Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.
-
8.发明申请公开(公告)号：US20120311277A1
公开(公告)日：2012-12-06
申请号：US13151101
申请日：2011-06-01
申请人： Michael H.M. Chu , Jeffrey Schulz , Chiakang Sung , Ravish Kapasi
发明人： Michael H.M. Chu , Jeffrey Schulz , Chiakang Sung , Ravish Kapasi
IPC分类号： G06F12/08
CPC分类号： G06F13/1626 , G06F13/16 , G06F13/1605 , G06F13/18
摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控制器。 存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。 为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。 优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。 优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。
-
公开(公告)号：US20050041668A1
公开(公告)日：2005-02-24
申请号：US10642310
申请日：2003-08-18
CPC分类号： H04L43/0888 , H04L12/14 , H04L12/1432 , H04L47/10 , H04L47/36 , H04L69/166 , H04L69/32
摘要： An apparatus for transferring data in a telecommunications network. The apparatus includes a memory in which a packet memory length is stored. The apparatus includes a mechanism for determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network. The apparatus includes a mechanism for sending the packet having the link length to the network. A method for transferring data in a telecommunications network. The method includes the steps of storing in a memory a memory length of a packet. There is the step of determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network There is the step of sending the packet having the link length to the network.
摘要翻译： 一种用于在电信网络中传送数据的装置。 该装置包括存储分组存储器长度的存储器。 该装置包括用于基于存储器长度和至少一个参数来确定将被发送到网络的分组的链路长度的机制，其中链路长度正确对应于分组在网络中的物理线路带宽使用。 该装置包括用于向网络发送具有链路长度的分组的机制。 一种用于在电信网络中传送数据的方法。 该方法包括在存储器中存储分组的存储器长度的步骤。 基于存储器长度和至少一个参数确定要发送到网络的分组的链路长度的步骤，其中链路长度正确对应于分组在网络中的物理线路带宽使用。步骤 将具有链路长度的分组发送到网络。
-
公开(公告)号：US07352751B2
公开(公告)日：2008-04-01
申请号：US10642310
申请日：2003-08-18
CPC分类号： H04L43/0888 , H04L12/14 , H04L12/1432 , H04L47/10 , H04L47/36 , H04L69/166 , H04L69/32
摘要： An apparatus for transferring data in a telecommunications network. The apparatus includes a memory in which a packet memory length is stored. The apparatus includes a mechanism for determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network. The apparatus includes a mechanism for sending the packet having the link length to the network. A method for transferring data in a telecommunications network. The method includes the steps of storing in a memory a memory length of a packet. There is the step of determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network There is the step of sending the packet having the link length to the network.
摘要翻译： 一种用于在电信网络中传送数据的装置。 该装置包括存储分组存储器长度的存储器。 该装置包括用于基于存储器长度和至少一个参数来确定将被发送到网络的分组的链路长度的机制，其中链路长度正确对应于分组在网络中的物理线路带宽使用。 该装置包括用于向网络发送具有链路长度的分组的机制。 一种用于在电信网络中传送数据的方法。 该方法包括在存储器中存储分组的存储器长度的步骤。 基于存储器长度和至少一个参数确定要发送到网络的分组的链路长度的步骤，其中链路长度正确对应于分组在网络中的物理线路带宽使用。步骤 将具有链路长度的分组发送到网络。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.013 秒)
