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    Power management of computer peripheral devices which determines non-usage of a device through usage detection of other devices
    1.
    发明授权
    Power management of computer peripheral devices which determines non-usage of a device through usage detection of other devices 有权
    通过其他设备的使用检测来确定设备不使用的计算机外围设备的电源管理

    公开(公告)号：US07685450B2

    公开(公告)日：2010-03-23

    申请号：US11674450

    申请日：2007-02-13

    Applicant: Drew J. Dutton ,  James R. MacDonald ,  Stephen Cox

    Inventor： Drew J. Dutton ,  James R. MacDonald ,  Stephen Cox

    IPC: G06F1/00

    CPC classification number: G06F1/3215

    Abstract: A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

    Abstract translation: 一种用于监视外围设备的使用并且当使用指示没有使用第二外围设备时将第二外围设备置于低功率状态的系统和方法。 例如，如果计算机系统检测到用户的当前打字率指示用户可能在键盘上具有双手，则计算机系统可以向计算机鼠标生成信号以进入低功率状态。 计算机系统可以使用用户的先前使用来确定当前使用情况何时指示第二外围设备未被使用。 在第二外围设备处于低功率状态之后，当计算机系统确定用户不再具有双手时，计算机系统可以向第二外围设备产生信号以返回到正常的功率状态。

    Associative noise attenuation
    2.
    发明授权
    Associative noise attenuation 失效
    相关噪声衰减

    公开(公告)号：US06825786B1

    公开(公告)日：2004-11-30

    申请号：US10430863

    申请日：2003-05-06

    Applicant: James R. MacDonald ,  Drew J. Dutton ,  Stephen Cox

    Inventor： James R. MacDonald ,  Drew J. Dutton ,  Stephen Cox

    IPC: H03M166

    CPC classification number: G10K11/178 ,  G10K2210/11 ,  G10K2210/3033 ,  G11B20/10009

    Abstract: A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.

    Abstract translation: 系统可以包括被配置为存储衰减波形和控制逻辑的存储器。 控制逻辑被配置为接收指示噪声源的操作特性的同步信号。 响应于同步信号的特性（例如，频率）的值，如果衰减波形与同步信号的特性值相关联，则控制逻辑被配置为从存储器输出衰减波形。 根据衰减波形产生的衰减噪声会衰减由噪声源产生的噪声。

    Cosine algorithm for relatively small angles
    3.
    发明授权
    Cosine algorithm for relatively small angles 失效
    余弦算法相对较小的角度

    公开(公告)号：US06434582B1

    公开(公告)日：2002-08-13

    申请号：US09336394

    申请日：1999-06-18

    Applicant: Gwangwoo Choe ,  James R. MacDonald

    Inventor： Gwangwoo Choe ,  James R. MacDonald

    IPC: G06F102

    CPC classification number: G06F7/5446

    Abstract: A system and method for computing the cosine of an input value. The system comprises a logical processing unit and an addition unit. The logical processing unit comprises an input bus with a plurality of input lines for receiving an input angle value. The logical processing unit includes a first plurality of gates, preferably AND gates, coupled to the input bus. Each gate of the first plurality of gates couples to two or more of the input lines. The logical processing unit generates N output operands on N corresponding output buses. At least one of the output buses includes (a) at least one output line coupled to an output of one of the first plurality of gates, and (b) at least one output line coupled to one of the input lines of the input bus. The number N of output buses is greater than or equal to two. The addition unit couples to the N output buses of the logical processing unit, and is configured to perform an addition of the N binary operands provided on the N output buses. The addition unit generates a resultant number which represents the cosine of the input operand conveyed on the input bus. The input angle value is assumed to have a predetermined number of leading zeros. In general, output lines are coupled to (a) input lines, (b) outputs of gates, or (c) set equal to zero.

    Abstract translation: 用于计算输入值的余弦的系统和方法。 该系统包括逻辑处理单元和加法单元。 逻辑处理单元包括具有用于接收输入角度值的多条输入线的输入总线。 逻辑处理单元包括耦合到输入总线的第一多个门，优选与门。 第一多个门的每个栅极耦合到两个或更多个输入线。 逻辑处理单元在N个对应的输出总线上产生N个输出操作数。 输出总线中的至少一个包括（a）耦合到第一多个门中的一个的输出的至少一个输出线，以及（b）耦合到输入总线的输入线之一的至少一个输出线。 输出总线数N大于或等于2。 加法单元耦合到逻辑处理单元的N个输出总线，并且被配置为执行在N个输出总线上提供的N个二进制操作数的相加。 加法单元生成表示在输入总线上传送的输入操作数的余弦的合成数。 假设输入角度值具有预定数量的前导零。 通常，输出线耦合到（a）输入线，（b）门的输出，或（c）设置为等于零。

    Real time interrupt handling for superscalar processors
    4.
    发明授权
    Real time interrupt handling for superscalar processors 失效
    超标量处理器的实时中断处理

    公开(公告)号：US6044430A

    公开(公告)日：2000-03-28

    申请号：US992283

    申请日：1997-12-17

    Applicant: James R. MacDonald

    Inventor： James R. MacDonald

    IPC: G06F9/48 ,  G06F12/12 ,  G06F9/46

    CPC classification number: G06F9/4812 ,  G06F12/126

    Abstract: A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order to execute the interrupt service routine. Instead of using the interrupt acknowledge cycles normally used to locate an interrupt vector, and then using the interrupt vector to locate an interrupt descriptor, the interrupt descriptor is stored in an RTI register coupled to the RTI control unit. In one embodiment, the CPU is configured not to save processor context upon initiation of a real time interrupt. Instead, as register resources are needed by the real time service routine, these resources are allocated. Registers allocated for real time use are indicated in the RTI register. In yet another embodiment, the CPU is configured with lockable cache lines in the instruction and data caches. An RTI bit is defined in the code and data segment descriptors for indicating whether or not the code/data within the segment is real time code/data (i.e. is used in an RTI service routine). The code/data within these segments is locked into the instruction and/or data cache. The cache replacement algorithm employed by the cache attempts to select a non-locked cache line for storing a cache line being transferred into the cache.

    Abstract translation: CPU包括被配置为控制CPU的实时中断能力的实时中断（RTI）控制单元。 在RTI接收到实时中断信号时，RTI控制单元在指令边界处中断当前正在执行的指令，以执行中断服务程序。 而不是使用通常用于定位中断向量的中断确认周期，然后使用中断向量来定位中断描述符，中断描述符被存储在连接到RTI控制单元的RTI寄存器中。 在一个实施例中，CPU被配置成在启动实时中断时不保存处理器上下文。 相反，由于实时服务程序需要注册资源，所以分配这些资源。 分配给实时使用的寄存器在RTI寄存器中指示。 在另一个实施例中，CPU在指令和数据高速缓存中配置有可锁定的高速缓存行。 在代码和数据段描述符中定义了一个RTI位，用于指示段内的代码/数据是否是实时代码/数据（即在RTI服务程序中使用）。 这些段中的代码/数据被锁定在指令和/或数据高速缓存中。 缓存器采用的高速缓存替换算法尝试选择非锁定高速缓存线，用于存储被传送到高速缓存中的高速缓存行。

    System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus
    7.
    发明授权
    System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus 失效
    通过分别在本地总线上驱动DMA配置寄存器的地址和存储地址来执行I / O访问和存储器访问的系统

    公开(公告)号：US5561821A

    公开(公告)日：1996-10-01

    申请号：US145375

    申请日：1993-10-29

    Applicant: Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

    Inventor： Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

    IPC: G06F13/28 ,  G06F13/36

    CPC classification number: G06F13/28

    Abstract: A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.

    Abstract translation: 提供了通过执行存储器访问周期和I / O访问周期来执行DMA传输的直接存储器访问控制器。 在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。 在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 DMA配置地址范围是映射DMA控制器的配置寄存器以接收初始化数据的地址值范围。 因此，可能连接到本地总线的其他外围设备将不会响应I / O访问周期。 不需要禁止地址禁止信号来禁用DMA传输中不涉及的其他I / O外围设备的地址解码器。 由于DMA传输的存储器访问周期和I / O访问周期与系统微处理器执行的存储器访问周期和I / O访问周期相同，因此子系统不需要响应专门的DMA协议。 最后，虽然DMA控制器实现了两个周期的DMA传输，但DMA控制器与传统的外围设备兼容，它们采用一个周期的DMA传输协议。

    Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller
    8.
    发明授权
    Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller 失效
    计算机系统在通过在DMA控制器中驱动本地总线上的范围内的地址来禁用非参与的外设的I / O寻址技术期间选择外围设备的字节通道

    公开(公告)号：US5561819A

    公开(公告)日：1996-10-01

    申请号：US145376

    申请日：1993-10-29

    Applicant: Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

    Inventor： Douglas D. Gephardt ,  Dan S. Mudgett ,  James R. MacDonald

    IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40

    CPC classification number: G06F13/28 ,  G06F13/4018

    Abstract: A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.

    Abstract translation: 直接存储器访问控制器通过执行存储器访问周期和I / O访问周期来实现用于执行所需DMA传输的两周期方法。 在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。 在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 在I + 544 O访问周期期间，编码地址值的较低的两位，以向外围设备提供字节通道信息。 外围设备响应地在指定的字节通道处接收或提供数据。 结果，可能连接到本地总线的外围设备将不会响应I / O访问周期，而编码字节通道信息被提供给期望的外围设备，而不需要专用字节选择线。

    Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility
    9.
    发明授权
    Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility 失效
    电源管理架构，包括用于传送编码的活动信号的电源管理消息总线，以获得最佳的灵活性

    公开(公告)号：US5493684A

    公开(公告)日：1996-02-20

    申请号：US223984

    申请日：1994-04-06

    Applicant: Douglas D. Gephardt ,  James R. MacDonald ,  Rita M. O'Brien

    Inventor： Douglas D. Gephardt ,  James R. MacDonald ,  Rita M. O'Brien

    IPC: G06F1/04 ,  G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/325 ,  G06F1/3287 ,  Y02B60/1217 ,  Y02B60/1282

    Abstract: An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit. The power management unit receives the encoded messages on the power management message bus and responsively makes decisions as to the appropriate power management mode to enter. The power management unit includes a clock control unit coupled to an internal clock generator of the integrated processor for controlling the frequencies of a CPU clock signal and a system clock signal. The power management unit further includes a power control unit for controlling the application of power to various external peripheral devices.

    Abstract translation: 提供了一种集成处理器，其包括耦合到诸如DMA控制器，中断控制器和定时器的各种片上外围设备的CPU核心。 集成处理器还包括耦合到DMA控制器，中断控制器和用于监视集成处理器的内部中断和总线请求信号的定时器的电源管理消息单元。 功率管理消息单元还可以监视集成处理器的其他选定的活动，例如浮点协处理子单元的活动。 基于所检测到的活动（如果有的话），功率管理消息单元对功率管理消息总线上的消息进行编码，从而向外部电源管理单元提供关于集成处理器的内部事件的信息。 电源管理决定由外部电源管理单元进行。 电源管理单元在电源管理消息总线上接收编码的消息，并且响应于作出关于进入的适当的电源管理模式的决定。 功率管理单元包括时钟控制单元，其耦合到集成处理器的内部时钟发生器，用于控制CPU时钟信号和系统时钟信号的频率。 电源管理单元还包括用于控制向各种外部外围设备施加电力的电力控制单元。

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