公开(公告)号：US20200044632A1

公开(公告)日：2020-02-06

申请号：US16051102

申请日：2018-07-31

Applicant: JACK R. POWELL, III ,  ALEXANDER LOUIS BRAUN

Inventor： JACK R. POWELL, III ,  ALEXANDER LOUIS BRAUN

IPC: H03K3/38 ,  H03K19/195 ,  G11C11/44 ,  H03K19/20

Abstract: A reciprocal quantum logic (RQL) phase-mode D flip-flop accepts a data input and a logical clock input. A D flip-flop with an enable input further accepts enable input and further requires that the enable be asserted high to allow the data input to change the output on the logical clock pulse. The flip-flop includes a storage loop and a comparator, each of which includes Josephson junctions (JJs). The storage loop stores the data input, provided as a positive or negative single flux quantum (SFQ) pulse, is stored in the storage loop as positive or negative state, respectively, effectively biasing a JJ shared between the storage loop and the comparator. The data input is captured to the output upon clocking (or enabled clocking), when a clock pulse causes the shared JJ to preferentially trigger over an escape JJ in the comparator, the shared JJ having been biased by storage loop current.

公开(公告)号：US10389361B1

公开(公告)日：2019-08-20

申请号：US16102385

申请日：2018-08-13

Applicant: Jack R. Powell, III ,  Alexander L. Braun

Inventor： Jack R. Powell, III ,  Alexander L. Braun

IPC: H03K19/195 ,  G06N99/00 ,  H03K19/177 ,  G11C11/44 ,  H01L39/02 ,  H03M7/00 ,  B82Y10/00 ,  G06N10/00

Abstract: Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.

公开(公告)号：US20190238137A1

公开(公告)日：2019-08-01

申请号：US16102385

申请日：2018-08-13

Applicant: JACK R. POWELL, III ,  ALEXANDER L. BRAUN

Inventor： JACK R. POWELL, III ,  ALEXANDER L. BRAUN

IPC: H03K19/195 ,  G06N10/00 ,  B82Y10/00 ,  H03M7/00 ,  H03K19/177 ,  G11C11/44 ,  H01L39/02

CPC classification number: H03K19/195 ,  B82Y10/00 ,  G06N10/00 ,  G11C11/44 ,  H01L39/025 ,  H03K19/17708 ,  H03K19/1952 ,  H03K19/1954 ,  H03M7/003

Abstract: Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.

公开(公告)号：US10103736B1

公开(公告)日：2018-10-16

申请号：US15886684

申请日：2018-02-01

Applicant: Jack R. Powell, III ,  Alexander L. Braun

Inventor： Jack R. Powell, III ,  Alexander L. Braun

IPC: H03K19/195 ,  G06N99/00 ,  H03K19/177 ,  G11C11/44 ,  H01L39/02 ,  H03M7/00 ,  B82Y10/00

Abstract: An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.